公开(公告)号：US20120009751A1

公开(公告)日：2012-01-12

申请号：US13237265

申请日：2011-09-20

申请人： Stephan Kronholz ,  Berthold Reimes ,  Richard Carter ,  Fernando Koch ,  Gisela Schammler

发明人： Stephan Kronholz ,  Berthold Reimes ,  Richard Carter ,  Fernando Koch ,  Gisela Schammler

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L21/28 ,  H01L21/8234

摘要： In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a selective epitaxial growth process without affecting the back side of the substrates. Consequently, any negative effects, such as contamination of substrates and process tools, reduced surface quality of the back side and the like, may be suppressed or reduced by providing a mask material and preserving the material at least during the selective epitaxial growth process.

摘要翻译： 在用于在早期制造阶段形成高k金属栅电极结构的复杂方法中，可以在选择性外延生长工艺的基础上沉积阈值调节半导体合金，而不会影响衬底的背面。 因此，至少在选择性外延生长过程中，可以通过提供掩模材料和保存材料来抑制或减少背面等的任何负面影响，例如衬底和工艺工具的污染，降低表面质量等。

公开(公告)号：US08071442B2

公开(公告)日：2011-12-06

申请号：US12552642

申请日：2009-09-02

申请人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

发明人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

IPC分类号： H01L21/8242

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

摘要翻译： 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层（例如二氧化硅材料）来维持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，P沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。

公开(公告)号：US20110156857A1

公开(公告)日：2011-06-30

申请号：US12905779

申请日：2010-10-15

申请人： Andreas Kurz ,  Stephan Kronholz ,  Roman Boschke

发明人： Andreas Kurz ,  Stephan Kronholz ,  Roman Boschke

IPC分类号： H01H37/76 ,  H01H69/02

CPC分类号： G11C17/16 ,  H01L21/823807 ,  H01L23/5256 ,  H01L27/0629 ,  H01L29/7833 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49107 ,  H01L2924/00

摘要： An electronic fuse may receive a silicon/germanium material in the fuse body, which in turn may result in the formation of a metal silicide material of reduced thickness. Consequently, the current density and, thus, the electromigration and heat generation in the metal silicide material may be increased for a given amount of current. Consequently, transistor switches for applying the programming pulse to the electronic fuse may be reduced in size.

摘要翻译： 电子保险丝可以在保险丝体中接收硅/锗材料，这又可能导致厚度减小的金属硅化物材料的形成。 因此，对于给定量的电流，可以增加金属硅化物材料中的电流密度以及因此的电迁移和发热。 因此，用于将编程脉冲施加到电子熔断器的晶体管开关的尺寸可以减小。

公开(公告)号：US20110156172A1

公开(公告)日：2011-06-30

申请号：US12908053

申请日：2010-10-20

申请人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

发明人： Stephan Kronholz ,  Maciej Wiatr ,  Roman Boschke ,  Peter Javorka

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66651

摘要： When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.

摘要翻译： 当形成需要用于一种类型的晶体管的阈值调节半导体合金的复杂的栅电极结构时，在相应的有源区中形成凹部，从而在半导体材料的沉积期间提供优异的工艺均匀性。 此外，在凹陷之后注入阱掺杂剂物质，从而避免不必要的掺杂剂损失。 由于凹槽，可以在选择性外延生长工艺期间避免有源区的任何暴露的侧壁表面区域，从而显着地有助于提高包括高k金属栅叠层的晶体管的阈值稳定性。

公开(公告)号：US20110024914A1

公开(公告)日：2011-02-03

申请号：US12844263

申请日：2010-07-27

申请人： Stephan Kronholz ,  Markus Lenski ,  Ralf Richter

发明人： Stephan Kronholz ,  Markus Lenski ,  Ralf Richter

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/8221 ,  H01L23/53276 ,  H01L27/0688 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/80001

摘要： In a stacked chip configuration, the “inter chip” connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips.

摘要翻译： 在堆叠式芯片配置中，基于功能分子建立“芯片间”连接，从而在不同半导体芯片之间提供快速且空间有效的通信。

公开(公告)号：US20100301421A1

公开(公告)日：2010-12-02

申请号：US12772436

申请日：2010-05-03

申请人： Stephan Kronholz ,  Markus Lenski ,  Vassilios Papageorgiou

发明人： Stephan Kronholz ,  Markus Lenski ,  Vassilios Papageorgiou

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51

摘要： Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.

摘要翻译： 基于嵌入式应变诱发半导体合金，可以通过基于高k介电材料与含金属盖层组合形成栅电极结构来增强P沟道晶体管的性能，以获得 栅电极结构的底切配置。 因此，应变诱导半导体合金可以基于最小厚度的侧壁间隔物形成，以便使应变诱导半导体材料更靠近沟道区的中心区域。

公开(公告)号：US09224863B2

公开(公告)日：2015-12-29

申请号：US13483481

申请日：2012-05-30

申请人： Peter Javorka ,  Stephan Kronholz ,  Gunda Beernink

发明人： Peter Javorka ,  Stephan Kronholz ,  Gunda Beernink

IPC分类号： H01L27/095 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/51

CPC分类号： H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834

摘要： In sophisticated semiconductor devices, transistors may be formed on the basis of a high-k metal gate electrode structure provided in an early manufacturing phase, wherein an efficient strain-inducing mechanism may be implemented by using an embedded strain-inducing semiconductor alloy. In order to reduce the number of lattice defects and provide enhanced etch resistivity in a critical zone, i.e., in a zone in which a threshold voltage adjusting semiconductor alloy and the strain-inducing semiconductor material are positioned in close proximity, an efficient buffer material or seed material, such as a silicon material, is incorporated, which may be accomplished during the selective epitaxial growth process.

摘要翻译： 在复杂的半导体器件中，可以在早期制造阶段提供的高k金属栅电极结构的基础上形成晶体管，其中可以通过使用嵌入式应变诱导半导体合金来实现有效的应变诱导机制。 为了减少晶格缺陷的数量并且在临界区域（即，阈值电压调节半导体合金和应变诱导半导体材料位于紧邻的区域）提供增强的蚀刻电阻率，可以使用有效的缓冲材料或 引入种子材料，例如硅材料，其可以在选择性外延生长过程期间完成。

公开(公告)号：US08969190B2

公开(公告)日：2015-03-03

申请号：US13593614

申请日：2012-08-24

申请人： Stephan Kronholz ,  Joachim Patzer

发明人： Stephan Kronholz ,  Joachim Patzer

IPC分类号： H01L21/44

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Disclosed herein are various methods of forming a layer of silicon on a layer of silicon/germanium. In one example, a method disclosed herein includes forming a silicon/germanium material on a semiconducting substrate, after forming the silicon/germanium material, performing a heating process to raise a temperature of the substrate to a desired silicon formation temperature while flowing a silicon-containing precursor and a chlorine-containing precursor into the deposition chamber during the heating process, and, after the temperature of the substrate reaches the desired silicon formation temperature, forming a layer of silicon on the silicon/germanium material.

摘要翻译： 本文公开了在硅/锗层上形成硅层的各种方法。 在一个实例中，本文公开的方法包括在形成硅/锗材料之后，在半导体衬底上形成硅/锗材料，执行加热过程以将衬底的温度升高到期望的硅形成温度， 并且在基板的温度达到所需的硅形成温度之后，在硅/锗材料上形成硅层。

公开(公告)号：US08939765B2

公开(公告)日：2015-01-27

申请号：US12965118

申请日：2010-12-10

申请人： Stephan Kronholz ,  Peter Javorka ,  Maciej Wiatr ,  Roman Boschke ,  Christian Krueger

发明人： Stephan Kronholz ,  Peter Javorka ,  Maciej Wiatr ,  Roman Boschke ,  Christian Krueger

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7843 ,  H01L29/7848

摘要： In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.

摘要翻译： 在复杂的半导体器件中，通常可以通过在P沟道晶体管的有源区中提供硅/锗材料相关联的缺陷率可以通过在选择性外延生长之前或期间引入碳物质而显着降低 硅/锗材料。 在一些实施方案中，可以在选择性生长过程中引入碳物质，而在其它情况下可以使用离子注入工艺。 在这种情况下，也可以在N沟道晶体管中获得优异的应变条件。

公开(公告)号：US08772843B2

公开(公告)日：2014-07-08

申请号：US13183549

申请日：2011-07-15

申请人： Stephan Kronholz ,  Markus Lenski ,  Kerstin Ruttloff ,  Volker Jaschke

发明人： Stephan Kronholz ,  Markus Lenski ,  Kerstin Ruttloff ,  Volker Jaschke

IPC分类号： H01L29/76 ,  H01L21/02 ,  H01L21/31 ,  H01L21/461 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

摘要： A silicon dioxide material may be provided in sophisticated semiconductor devices in the form of a double liner including an undoped silicon dioxide material in combination with a high density plasma silicon dioxide, thereby providing reduced dependency on pattern density. In some illustrative embodiments, the silicon dioxide double liner may be used as a spacer material and as a hard mask material in process strategies for incorporating a strain-inducing semiconductor material.

摘要翻译： 可以在复合半导体器件中提供二氧化硅材料，其形式为双层衬垫，其包括与高密度等离子体二氧化硅组合的未掺杂二氧化硅材料，从而降低对图案密度的依赖性。 在一些说明性实施例中，二氧化硅双层衬垫可以用作间隔材料，并且可用作掺入应变诱导半导体材料的工艺策略中的硬掩模材料。