公开(公告)号：US12230690B2

公开(公告)日：2025-02-18

申请号：US18360694

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Wei Yao ,  Chen-Ju Yu ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/20 ,  H01L29/267 ,  H01L29/417 ,  H01L29/43 ,  H01L29/778

Abstract: The transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer.

公开(公告)号：US20230369449A1

公开(公告)日：2023-11-16

申请号：US18360694

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Wei Yao ,  Chen-Ju Yu ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/10 ,  H01L29/43 ,  H01L29/267 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/1066 ,  H01L29/432 ,  H01L29/267 ,  H01L21/02271 ,  H01L29/41766 ,  H01L2924/0002

Abstract: The transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer.

公开(公告)号：US10522630B2

公开(公告)日：2019-12-31

申请号：US16386583

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Wei Yao ,  Chun-Wei Hsu ,  Chen-Ju Yu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Chih-Wen Hsiung ,  King-Yuen Wong

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.

公开(公告)号：US10510601B2

公开(公告)日：2019-12-17

申请号：US16114932

申请日：2018-08-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ling-Fu Nieh ,  Chun-Wei Hsu ,  Pinlei Edmund Chu ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Yi-Sheng Lin

IPC: H01L21/768 ,  H01L29/78 ,  H01L21/321 ,  H01L21/8238 ,  H01L23/485 ,  H01L29/08 ,  C09G1/02

Abstract: A method of manufacturing a device includes exposing at least one of a source/drain contact plug or a gate contact plug to a metal ion source solution during a manufacturing process, wherein a constituent metal of a metal ion in the metal ion source solution and the at least one source/drain contact plug or gate contact plug is the same. If the source/drain contact plug or the gate contact plug is formed of cobalt, the metal ion source solution includes a cobalt ion source solution. If the source/drain contact plug or the gate contact plug is formed of tungsten, the metal ion source solution includes a tungsten ion source solution.

公开(公告)号：US20190245046A1

公开(公告)日：2019-08-08

申请号：US16386583

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Wei Yao ,  Chun-Wei Hsu ,  Chen-Ju Yu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Chih-Wen Hsiung ,  King-Yuen Wong

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a carrier channel layer at an interface of the first layer and the second layer. The transistor additionally includes a gate structure, a drain, and a source over the second layer. The transistor also includes a passivation material in the second layer between an edge of the gate structure and an edge of the drain in a top-side view. The carrier channel layer has a smaller surface area than the first layer between the edge of the gate structure and the edge of the drain in the top-side view.

公开(公告)号：US20190096761A1

公开(公告)日：2019-03-28

申请号：US16114932

申请日：2018-08-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ling-Fu Nieh ,  Chun-Wei Hsu ,  Pinlei Edmund Chu ,  Chi-Jen Liu ,  Liang-Guang Chen ,  Yi-Sheng Lin

IPC: H01L21/768 ,  H01L29/78 ,  H01L21/321 ,  H01L21/8238 ,  H01L23/485 ,  H01L29/08

Abstract: A method of manufacturing a device includes exposing at least one of a source/drain contact plug or a gate contact plug to a metal ion source solution during a manufacturing process, wherein a constituent metal of a metal ion in the metal ion source solution and the at least one source/drain contact plug or gate contact plug is the same. If the source/drain contact plug or the gate contact plug is formed of cobalt, the metal ion source solution includes a cobalt ion source solution. If the source/drain contact plug or the gate contact plug is formed of tungsten, the metal ion source solution includes a tungsten ion source solution.

公开(公告)号：US09793371B2

公开(公告)日：2017-10-17

申请号：US15238083

申请日：2016-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Po-Chih Chen ,  King-Yuen Wong ,  Jiun-Lei Jerry Yu ,  Fu-Wei Yao ,  Chen-Ju Yu

IPC: H01L21/338 ,  H01L29/66 ,  H01L29/267 ,  H01L29/43 ,  H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/205 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/66462 ,  H01L29/0653 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/432 ,  H01L29/7786 ,  H01L29/7787

Abstract: A method of forming a high electron mobility transistor (HEMT) includes forming a second III-V compound layer on a first III-V compound layer, forming a source feature and a drain feature on the second III-v compound layer, depositing a p-type layer on a portion of the second III-V compound layer between the source feature and the drain feature, and forming a gate electrode on the p-type layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer.

公开(公告)号：US20160359015A1

公开(公告)日：2016-12-08

申请号：US15238083

申请日：2016-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Wei Hsu ,  Po-Chih Chen ,  King-Yuen Wong ,  Jiun-Lei Jerry Yu ,  Fu-Wei Yao ,  Chen-Ju Yu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/66462 ,  H01L29/0653 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/432 ,  H01L29/7786 ,  H01L29/7787

Abstract: A method of forming a high electron mobility transistor (HEMT) includes forming a second III-V compound layer on a first III-V compound layer, forming a source feature and a drain feature on the second III-v compound layer, depositing a p-type layer on a portion of the second III-V compound layer between the source feature and the drain feature, and forming a gate electrode on the p-type layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer.

Abstract translation: 形成高电子迁移率晶体管（HEMT）的方法包括在第一III-V化合物层上形成第二III-V化合物层，在第二III-v化合物层上形成源特征和漏极特征，沉积p 在源特征和漏极特征之间的第二III-V化合物层的一部分上形成p型层，并在p型层上形成栅电极。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。

公开(公告)号：US09425300B2

公开(公告)日：2016-08-23

申请号：US14465250

申请日：2014-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Ju Yu ,  Fu-Wei Yao ,  Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Chih-Wen Hsiung

IPC: H01L29/778 ,  H01L21/335 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is over the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located at an interface of the first III-V compound layer and the second III-V compound layer. A dielectric cap layer is over the second III-V compound layer and a protection layer is over the dielectric cap layer. Slanted field plates are in a combined opening in the dielectric cap layer and protection layer.

Abstract translation: 半导体结构包括第一III-V族化合物层。 第二个III-V化合物层在第一个III-V化合物层之上，并且与组合物中的第一个III-V化合物层不同。 载体通道位于第一III-V化合物层和第二III-V化合物层的界面处。 电介质盖层位于第二III-V化合物层之上，保护层位于电介质盖层之上。 倾斜的场板位于电介质盖层和保护层中的组合开口中。

公开(公告)号：US09385225B2

公开(公告)日：2016-07-05

申请号：US14547770

申请日：2014-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Ju Yu ,  Chih-Wen Hsiung ,  Fu-Wei Yao ,  Chun-Wei Hsu ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang

IPC: H01L29/788 ,  H01L29/778 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/0661 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/30621 ,  H01L21/3065 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

Abstract: A method of making a circuit structure includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain.

Abstract translation: 制造电路结构的方法包括在衬底上生长本体层，以及在本体层上生长施主供体层。 该方法还包括在供体供体层上沉积掺杂层，以及图案化掺杂层以形成多个岛。 该方法还包括在供体供体层上形成栅极结构，其中栅极结构部分地位于多个岛的最大岛上。 该方法还包括在供体供体层上形成漏极，其中多个岛中的至少一个岛在栅极结构和漏极之间。