公开(公告)号：US20230253435A1

公开(公告)日：2023-08-10

申请号：US17735420

申请日：2022-05-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Chang Chang ,  Shih-Wei Lin ,  Te-Hsien Hsieh ,  Jung-I Lin

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14636 ,  H01L27/14683

Abstract: The present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material region. A second semiconductor material region is disposed onto the substrate. A patterned doped layer is arranged between the substrate and the second semiconductor material region. The second semiconductor material region includes a sidewall connecting to a bottom surface of the second semiconductor material region. The sidewall extends through the patterned doped layer. A bottom surface of the second semiconductor material region is directly over the photodiode region.

公开(公告)号：US10103122B2

公开(公告)日：2018-10-16

申请号：US15689982

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L21/30 ,  H01L21/46 ,  H01L23/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

公开(公告)号：US20150287694A1

公开(公告)日：2015-10-08

申请号：US14725266

申请日：2015-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/74 ,  H01L24/94 ,  H01L2224/02215 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/80004 ,  H01L2224/80007 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/80097 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83889 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/15 ,  Y10T156/1744 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2924/05442 ,  H01L2924/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Abstract translation: 公开了用于半导体晶片的混合键合系统和方法。 在一个实施例中，用于半导体晶片的混合键合系统包括腔室和设置在腔室内的多个子腔室。 机器人处理器设置在腔室内，其适于移动多个子室内的室内的多个半导体晶片。 多个子室包括适于从多个半导体晶片去除保护层的第一子室，以及适于在混合结合多个半导体之前激活多个半导体晶片的顶表面的第二子室 晶圆在一起 多个子室还包括适于对准多个半导体晶片并将多个半导体晶片混合地结合在一起的第三子室。

公开(公告)号：US20230299217A1

公开(公告)日：2023-09-21

申请号：US18311292

申请日：2023-05-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hao Chiang ,  Shih-Wei Lin ,  Eugene I-Chun Chen ,  Yi-Chen Chen

IPC: H01L31/0232 ,  H01L31/028 ,  H01L31/18 ,  G02B6/12 ,  G02B6/136 ,  G02B6/13 ,  G02B6/124

CPC classification number: H01L31/02327 ,  H01L31/028 ,  H01L31/1808 ,  G02B6/12004 ,  G02B6/136 ,  G02B6/131 ,  G02B6/124 ,  G02B2006/12107 ,  G02B2006/12061

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector.

公开(公告)号：US11714299B2

公开(公告)日：2023-08-01

申请号：US17556006

申请日：2021-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Wei Lin ,  Ming Chyi Liu

IPC: G02F1/01 ,  G02F1/225 ,  G02B6/12

CPC classification number: G02F1/011 ,  G02F1/0147 ,  G02F1/2257 ,  G02B2006/12142 ,  G02F2203/50

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a waveguide and a heater structure. The waveguide is disposed on a substrate and comprises an active region that extends continuously along a first distance. The heater structure overlies the waveguide. The heater structure comprises a conductive structure over the active region and a vertical structure disposed between the conductive structure and the substrate. The vertical structure comprises a conductive upper vertical segment and a lower vertical segment. The conductive structure and the conductive upper vertical segment continuously laterally extend across a second distance that is greater than or equal to the first distance. The first distance is greater than a width of the conductive structure.

公开(公告)号：US10354972B2

公开(公告)日：2019-07-16

申请号：US16160572

申请日：2018-10-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Liu ,  Shih-Wei Lin ,  Xin-Hua Huang ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L23/00

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

公开(公告)号：US09023674B2

公开(公告)日：2015-05-05

申请号：US14033089

申请日：2013-09-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Cheng Shen ,  Yi-Hsien Chang ,  Shih-Wei Lin ,  Chun-Ren Cheng

IPC: H01L21/00 ,  G01N27/414

CPC classification number: G01N27/4145 ,  G01N27/4148

Abstract: The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET includes a microwells having a sensing layer, a top metal stack under the sensing layer, and a multi-layer interconnect (MLI) under the top metal stack. The top metal stack includes a top metal and a protective layer over and peripherally surrounding the top metal.

Abstract translation: 本公开提供了生物场效应晶体管（BioFET）和制造BioFET器件的方法。 该方法包括使用与互补金属氧化物半导体（CMOS）工艺兼容或典型的一个或多个工艺步骤形成BioFET。 BioFET包括具有感测层的微孔，感测层下的顶部金属堆叠，以及在顶部金属堆叠下的多层互连（MLI）。 顶部金属堆叠包括顶部金属和保护层，并且围绕顶部金属周围。

公开(公告)号：US20140308752A1

公开(公告)日：2014-10-16

申请号：US13946782

申请日：2013-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Hsien Chang ,  Wei-Cheng Shen ,  Shih-Wei Lin ,  Chun-Ren Cheng

IPC: G01N27/414

CPC classification number: G01N27/4145 ,  Y10T436/143333

Abstract: The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a plurality of microwells having a bio-sensing layer and a number of stacked well portions over a multi-layer interconnect (MLI). A bottom surface area of a well portion is different from a top surface area of a well portion directly below. The microwells are formed by removing a top metal plate on a topmost level of the MLI.

Abstract translation: 本公开提供了生物场效应晶体管（BioFET）和制造BioFET器件的方法。 该方法包括使用与互补金属氧化物半导体（CMOS）工艺兼容或典型的一个或多个工艺步骤形成BioFET。 BioFET器件包括在多层互连（MLI）上具有生物感测层和多个堆叠阱部分的多个微孔。 井部的底面积与直接在下方的井口部的顶面积不同。 通过去除MLI的最上层的顶部金属板来形成微孔。