公开(公告)号：US10354973B2

公开(公告)日：2019-07-16

申请号：US16037537

申请日：2018-07-17

Applicant: TDK CORPORATION

Inventor： Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.

公开(公告)号：US10163847B2

公开(公告)日：2018-12-25

申请号：US15449361

申请日：2017-03-03

Applicant: TDK CORPORATION

Inventor： Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.

公开(公告)号：US20180175494A1

公开(公告)日：2018-06-21

申请号：US15840192

申请日：2017-12-13

Applicant: TDK Corporation

Inventor： Yuhei Horikawa ,  Makoto Orikasa ,  Yoshihiro Kanbayashi ,  Hisayuki Abe ,  Hirohumi Asou ,  Kosuke Kunitsuka

IPC: H01Q1/38 ,  H01Q1/22 ,  H01Q7/00

CPC classification number: H01Q1/38 ,  H01Q1/2208 ,  H01Q1/2225 ,  H01Q7/00 ,  H04B5/0031 ,  H04B5/0081

Abstract: Disclosed herein is a wiring component that includes a base material and a planar coil pattern formed on the base material. The planar coil pattern includes a coil wiring portion having one end, other end, and first to third connecting positions, the second connecting position being closer to the other end compared with the first connecting position, the third connecting position being closer to the one end compared with the second connecting position; a power-feed wiring portion connected to the first connecting position; and a connection wiring portion that short-circuits the second connecting position and the third connecting position. A cross-section structure of the planar coil pattern has a base resin layer formed on the base material, and a conductive layer formed on the base resin layer.

公开(公告)号：US09818736B1

公开(公告)日：2017-11-14

申请号：US15449074

申请日：2017-03-03

Applicant: TDK CORPORATION

Inventor： Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13611 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: A method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a smooth surface formation process of forming a smooth surface on the microbump, a lamination process of laminating three or more of the semiconductor chips by overlaying the microbump of one of the semiconductor chips on the microbump of another one of the semiconductor chips, and a bonding process of bonding the semiconductor chips to each other via the microbumps by heating to melt the microbumps, in which in the lamination process, of one of the semiconductor chips and another one of the semiconductor chips, the smooth surface is formed on at least one of the microbump, and one of the microbump contacts another one of the microbump on the smooth surface.

公开(公告)号：US09640500B2

公开(公告)日：2017-05-02

申请号：US13960173

申请日：2013-08-06

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: The present invention relates to a terminal structure comprising; a base material 10; an external electrode 20 formed on the base material; an insulating coating layer 30 formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal layer 70 filling the opening and covering part of the insulating coating layer; and a dome-shaped bump 85 covering the under-bump metal layer, wherein in a cross section along a lamination direction, the under-bump metal layer has a convex shape toward the bump, and the thickness Tu0 of the under-bump metal layer at a center of the opening is equal to or greater than the thickness Tu1 of the under-bump metal layer at an end portion of the opening.

公开(公告)号：US09070606B2

公开(公告)日：2015-06-30

申请号：US13960228

申请日：2013-08-06

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/485 ,  H01L23/492 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05552

Abstract: The present invention relates to a terminal structure comprising: a base material 10; an external electrode 20 formed on the base material; an insulating coating layer 30 formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal layer 70 filling the opening and covering part of the insulating coating layer; and a dome-shaped bump 85 covering the under-bump metal layer, wherein in a cross section along a lamination direction, a height Hbm at which the bump has a maximum diameter (Lbm) is lower than a maximum height Hu of the under-bump metal layer.

Abstract translation: 本发明涉及一种端子结构，包括：基材10; 形成在基材上的外部电极20; 绝缘涂层30，形成在基材和电极上，并具有露出电极的至少一部分的开口; 填充绝缘涂层的开口和覆盖部分的凸块下金属层70; 以及覆盖凸块下金属层的圆顶状凸起85，其中在沿着层叠方向的截面中，所述凸块具有最大直径（Lbm）的高度Hbm低于所述凸块下凸块的最大高度Hu， 凸块金属层。

公开(公告)号：US08976076B2

公开(公告)日：2015-03-10

申请号：US13790803

申请日：2013-03-08

Applicant: TDK Corporation

Inventor： Kenichi Yoshida ,  Yuhei Horikawa

IPC: H01Q1/36 ,  H01P3/08 ,  H01Q1/50 ,  H01P11/00

CPC classification number: H01P3/08 ,  H01P11/003 ,  H01Q1/36 ,  H01Q1/50

Abstract: A high-frequency transmission line having low alternate current (AC) resistance is provided. One aspect of the present invention is a high-frequency transmission line disposed along a surface of an insulating support, wherein, letting F [Hz] be the frequency of an AC electric signal transmitted by the high-frequency transmission line and Ms [Wb/m] be the saturation magnetization per unit area, the frequency value F and the saturation magnification value per unit area Ms satisfy the following expression (1): Ms≦(1.5×102)/F+5.7×10−8  (1).

Abstract translation: 提供具有低交流（AC）电阻的高频传输线。 本发明的一个方面是沿着绝缘支撑体的表面布置的高频传输线，其中，使F [Hz]为由高频传输线发送的AC电信号的频率，Ms [Wb / m]为每单位面积的饱和磁化强度，每单位面积Ms的频率值F和饱和倍率值满足下式（1）：Ms＆nlE;（1.5×102）/ F +5.7×10-8（1）。