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公开(公告)号:US10784188B2
公开(公告)日:2020-09-22
申请号:US16443653
申请日:2019-06-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Rongwei Zhang , Vikas Gupta
IPC: H01L23/495 , H01L23/00 , H01L21/48
Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.
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公开(公告)号:US20200185322A1
公开(公告)日:2020-06-11
申请号:US16213557
申请日:2018-12-07
Applicant: Texas Instruments Incorporated
Inventor: Rongwei Zhang , Vikas Gupta
IPC: H01L23/498 , H01L23/00 , H01L21/48
Abstract: In a described example, a packaged device includes a substrate having a device mounting surface with conductive lands having a first thickness spaced from one another on the device mounting surface. A first polymer layer is disposed on the device mounting surface between the conductive lands having a second thickness equal to the first thickness. The conductive lands have an outer surface not covered by the first polymer layer. A second polymer layer is disposed on the first polymer layer, the outer surface of the conductive lands not covered by the second polymer layer. Conductive nanoparticle material is disposed on the outer surface of the conductive lands. A third polymer layer is disposed on the second polymer layer between the conductive nanoparticle material on the conductive lands. At least one semiconductor device die is mounted to the third polymer layer having electrical terminals bonded to the conductive nanoparticle material.
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公开(公告)号:US20190304881A1
公开(公告)日:2019-10-03
申请号:US16443653
申请日:2019-06-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Rongwei Zhang , Vikas Gupta
IPC: H01L23/495 , H01L21/48 , H01L23/00
Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.
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公开(公告)号:US10312212B2
公开(公告)日:2019-06-04
申请号:US14541208
申请日:2014-11-14
Applicant: Texas Instruments Incorporated
Inventor: Rongwei Zhang
IPC: B82Y10/00 , B82Y40/00 , H01L23/00 , H01L23/495 , H01L29/06
Abstract: An apparatus for enhancing the thermal performance of semiconductor packages effectively. The concept of this invention is to provide silicon nanowires on the backside of an integrated circuit die to directly attach the die to the substrate, thereby improving the interface between die and substrate, and thus enhancing thermal performance and enhancing reliability by improving adhesion.
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公开(公告)号:US20180277463A1
公开(公告)日:2018-09-27
申请号:US15973828
申请日:2018-05-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Rongwei Zhang , Vikas Gupta
IPC: H01L23/495 , H01L21/48 , H01L23/00
CPC classification number: H01L23/49513 , H01L23/49541 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/743 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2224/05554 , H01L2224/05624 , H01L2224/27318 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/83192 , H01L2224/83194 , H01L2224/83855 , H01L2224/83951 , H01L2224/85203 , H01L2224/92247 , H01L2924/07811 , H01L2924/181 , H01L2924/00015 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.
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公开(公告)号:US20170365575A1
公开(公告)日:2017-12-21
申请号:US15690074
申请日:2017-08-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Yong Lin , Vikas Gupta , Rongwei Zhang
IPC: H01L23/00 , H01L21/56 , H01L23/544 , H01L23/31 , H01L21/304 , H01L23/495 , H01L21/48 , H01L21/78
CPC classification number: H01L24/29 , H01L21/304 , H01L21/4825 , H01L21/561 , H01L21/565 , H01L21/78 , H01L23/3107 , H01L23/3114 , H01L23/481 , H01L23/49503 , H01L23/49517 , H01L23/4952 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L23/544 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/32 , H01L24/48 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2221/68327 , H01L2223/54426 , H01L2223/54453 , H01L2224/13101 , H01L2224/16245 , H01L2224/27318 , H01L2224/2732 , H01L2224/27848 , H01L2224/29034 , H01L2224/29101 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29169 , H01L2224/2929 , H01L2224/32245 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/81815 , H01L2224/83801 , H01L2224/8385 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2924/014 , H01L2924/0665 , H01L2924/00
Abstract: A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.
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公开(公告)号:US20170162530A1
公开(公告)日:2017-06-08
申请号:US15368413
申请日:2016-12-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Yong Lin , Vikas Gupta , Rongwei Zhang
CPC classification number: H01L24/29 , H01L21/304 , H01L21/4825 , H01L21/561 , H01L21/565 , H01L21/78 , H01L23/3107 , H01L23/3114 , H01L23/481 , H01L23/49503 , H01L23/49517 , H01L23/4952 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L23/544 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/32 , H01L24/48 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2221/68327 , H01L2223/54426 , H01L2223/54453 , H01L2224/13101 , H01L2224/16245 , H01L2224/27318 , H01L2224/2732 , H01L2224/27848 , H01L2224/29034 , H01L2224/29101 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29169 , H01L2224/2929 , H01L2224/32245 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/81815 , H01L2224/83801 , H01L2224/8385 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2924/014 , H01L2924/0665
Abstract: A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.
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公开(公告)号:US09214440B1
公开(公告)日:2015-12-15
申请号:US14573071
申请日:2014-12-17
Applicant: Texas Instruments Incorporated
Inventor: Rongwei Zhang , Abram Castro
IPC: H01L23/495 , H01L23/00
CPC classification number: H01L23/49513 , H01L21/4825 , H01L21/565 , H01L23/3114 , H01L23/3121 , H01L23/3142 , H01L23/49541 , H01L23/49582 , H01L23/49586 , H01L23/562 , H01L24/03 , H01L24/04 , H01L24/26 , H01L24/28 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L2224/2919 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/73265 , H01L2224/83055 , H01L2224/83075 , H01L2224/83385 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/83862 , H01L2224/92247 , H01L2924/35121 , H01L2924/00012 , H01L2924/00 , H01L2924/00014 , H01L2924/0665 , H01L2924/0635
Abstract: The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating said top surface of said leadframe with first and second silane coating; heating said silane coatings to form a sol-gel layer having a porosity of at least 10%; applying a die to said sol-gel layer; securing said die to said sol-gel layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding.
Abstract translation: 本发明涉及一种用于抑制或防止在芯片附着/模具化合物与半导体器件的芯片焊盘和由这种方法形成的半导体器件的界面处的分层的方法。 该方法包括:提供具有顶表面的引线框架; 用第一和第二硅烷涂层涂覆所述引线框架的所述顶表面; 加热所述硅烷涂层以形成孔隙率至少为10%的溶胶 - 凝胶层; 将模头应用于所述溶胶 - 凝胶层; 通过模具附着化合物将所述模头固定到所述溶胶 - 凝胶层; 并且在固着芯片附着材料和引线接合之后,通过成型施加模塑料。
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公开(公告)号:US12199008B2
公开(公告)日:2025-01-14
申请号:US17219602
申请日:2021-03-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Jaimal Mallory Williamson , Rongwei Zhang
IPC: H01L23/373 , H01L23/00 , H01L23/31
Abstract: In examples, a semiconductor package comprises a substrate including a conductive layer; a conductive pillar coupled to the conductive layer; and a semiconductor die having first and second opposing surfaces. The first surface is coupled to the conductive pillar. The package also includes a die attach film abutting the second surface of the semiconductor die and a metal layer abutting the die attach film and having a metal layer surface facing away from the die attach film. The metal layer surface is exposed to an exterior of the FCCSP. The package includes a mold compound layer covering the substrate.
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公开(公告)号:US20240332119A1
公开(公告)日:2024-10-03
申请号:US18740444
申请日:2024-06-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Rongwei Zhang , Woochan Kim , Patrick Francis Thompson
IPC: H01L23/367 , H01L21/48 , H01L23/00 , H01L25/065
CPC classification number: H01L23/3677 , H01L21/4882 , H01L24/48 , H01L25/0655 , H01L2224/48138 , H01L2224/48158
Abstract: An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.
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