公开(公告)号：US10319809B2

公开(公告)日：2019-06-11

申请号：US15843444

申请日：2017-12-15

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L23/485 ,  H01L29/423

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

公开(公告)号：US20190051721A1

公开(公告)日：2019-02-14

申请号：US16163606

申请日：2018-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Hideaki Kawahara ,  Sameer P. Pendharkar

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3205 ,  H01L29/08 ,  H01L27/06 ,  H01L21/265

Abstract: Embodiments of a deep trench capacitor are disclosed. In one example a plurality of deep trenches is located in a first region of a semiconductor wafer, the first region having a first conductivity type. A corresponding dielectric layer is located on a surface of each of the plurality of deep trenches, and a corresponding doped polysilicon filler is located within each of the dielectric layers. Dielectric-filled trenches are located between each of the dielectric layers and the surface of the semiconductor wafer.

公开(公告)号：US10134830B2

公开(公告)日：2018-11-20

申请号：US15264147

申请日：2016-09-13

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Hideaki Kawahara ,  Sameer P. Pendharkar

IPC: H01L49/02 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L29/08 ,  H01L21/306 ,  H01L29/06 ,  H01L27/06

Abstract: A deep trench capacitor and a method for providing the same in a semiconductor process are disclosed. The method includes forming a plurality of deep trenches in a first region of a semiconductor wafer, the first region having well doping of a first type. A dielectric layer is formed on a surface of the plurality of deep trenches and a doped polysilicon layer is deposited to fill the plurality of deep trenches, with the doped polysilicon being doped with a dopant of a second type. Shallow trench isolation is formed overlying the dielectric layer at an intersection of the dielectric layer with the surface of the semiconductor wafer.

公开(公告)号：US09608088B2

公开(公告)日：2017-03-28

申请号：US14284696

申请日：2014-05-22

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. Pendharkar ,  John Lin

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/66681 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7816

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

公开(公告)号：US09583579B2

公开(公告)日：2017-02-28

申请号：US15191656

申请日：2016-06-24

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Sameer P. Pendharkar ,  Jarvis Benjamin Jacobs

IPC: H01L27/108 ,  H01L29/40

CPC classification number: H01L29/41 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/763 ,  H01L28/20 ,  H01L28/40 ,  H01L29/407 ,  H01L29/45 ,  H01L29/945

Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

Abstract translation: 半导体器件通过在衬底中形成深沟槽和在深沟槽的侧壁上形成介电衬垫来形成。 第一未掺杂多晶硅层形成在半导体器件上，延伸到电介质衬垫上的深沟槽中，但不填充深沟槽。 将掺杂剂注入到第一多晶硅层中。 在第一多晶硅层上形成第二层多晶硅。 热驱动退火激活并扩散掺杂剂。 在一个版本中，在形成第一多晶硅层之前，在深沟槽的底部去除电介质衬垫，使得深沟槽中的多晶硅提供与衬底的接触。 在另一种形式中，深沟槽中的多晶硅通过电介质衬垫从衬底隔离。

公开(公告)号：US20160254346A1

公开(公告)日：2016-09-01

申请号：US14634801

申请日：2015-02-28

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  John Lin ,  Guru Mathur ,  Scott G. Balster ,  Constantin Bulucea ,  Zachary K. Lee ,  Sameer P. Pendharkar

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

Abstract translation: 半导体器件包含在漏极漂移区域上具有横向n型漏极漂移区域和p型RESURF区域的LDNMOS晶体管。 RESURF区域延伸到半导体器件的衬底的顶表面。 半导体器件包括电耦合在RESURF区域和LDNMOS晶体管的低电压节点之间的分流器。 分路可以是RESURF层和LDNMOS晶体管的主体之间的衬底中的p型注入层，并且可以与RESURF层同时注入。 分流器可以穿过漏极漂移区域中的从RESURF层到漏极漂移区域下方的衬底的开口。 分路可以包括包括触点和金属互连线的金属互连元件。

公开(公告)号：US20150311281A1

公开(公告)日：2015-10-29

申请号：US14555330

申请日：2014-11-26

Applicant: Texas Instruments Incorporated

Inventor： Sameer P. Pendharkar ,  Binghua Hu ,  Henry Litzmann Edwards

IPC: H01L29/06 ,  H01L21/266 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324 ,  H01L29/167 ,  H01L21/265

CPC classification number: H01L29/0623 ,  H01L21/02164 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/324 ,  H01L21/74 ,  H01L29/0646 ,  H01L29/167 ,  H01L29/456

Abstract: A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer.

Abstract translation: 半导体器件具有通过以高剂量和低能量将锑和/或砷注入p型第一外延层而形成的n型掩埋层，并且以低剂量和高能量注入磷。 热驱动过程扩散并激活重掺杂物和磷。 锑和砷不会显着扩散，保持埋层主层的狭窄轮廓。 磷扩散以提供在主层下面几微米厚的轻掺杂层。 在掩埋层上生长外延p型层。

公开(公告)号：US20150187934A1

公开(公告)日：2015-07-02

申请号：US14578710

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7831

Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.

Abstract translation: 一种具有多个电流通道的LDMOS晶体管的集成电路和方法。 第一电流通道在掩埋的p型扩散之上，并且第二个电流通道在掩埋的p型扩散之下。

公开(公告)号：US10937905B2

公开(公告)日：2021-03-02

申请号：US14286202

申请日：2014-05-23

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Philip L. Hower ,  Sameer P. Pendharkar ,  John Lin ,  Guru Mathur ,  Scott Balster ,  Victor Sinow

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/761 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.

公开(公告)号：US10601422B2

公开(公告)日：2020-03-24

申请号：US15809291

申请日：2017-11-10

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03K17/687 ,  H01L29/06 ,  H03K19/0185 ,  H01L29/78 ,  H01L29/10 ,  H03K17/12 ,  H01L27/092 ,  H01L21/8238

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.