公开(公告)号：US20170185139A1

公开(公告)日：2017-06-29

申请号：US15016449

申请日：2016-02-05

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/32 ,  G06F3/06

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3287 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0688 ,  Y02D10/154 ,  Y02D10/171 ,  Y02D50/20

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

公开(公告)号：US20160217840A1

公开(公告)日：2016-07-28

申请号：US15089607

申请日：2016-04-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C7/22 ,  G06F9/44 ,  G11C14/00 ,  G06F1/32

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

Abstract translation: 处理设备的设计和操作可配置为在非易失性存储器恢复机器状态期间优化唤醒时间和峰值功耗成本。 处理装置包括被配置为存储由处理装置的多个易失性存储元件表示的机器状态的多个非易失性逻辑元件阵列。 将存储的机器状态从多个非易失性逻辑元件阵列读出到多个易失性存储元件。 在制造期间，非易失性逻辑元件阵列中每行的数行和数位数是基于目标唤醒时间和峰值功率成本的。 在另一种方法中，可以并行，顺序地或以任何组合来对数据进行数据写入或读取数据，以优化操作特性。

公开(公告)号：US09018976B2

公开(公告)日：2015-04-28

申请号：US14080183

申请日：2013-11-14

Applicant: Texas Instruments Incorporated

Inventor： Steven C. Bartling ,  Sudhanshu Khanna

IPC: H03K19/173

CPC classification number: H03K19/1735 ,  H03K3/356008

Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口正电平敏感复位预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，预置控制信号PRE为低电平，静止控制信号REN为高电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET和RETN，预置控制信号PRE和控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，PRE，REN，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号RET和RETN确定数据是否存储在双端口锁存器中。

公开(公告)号：US20150054557A1

公开(公告)日：2015-02-26

申请号：US14447911

申请日：2014-07-31

Applicant: Texas Instruments Incorporated

Inventor： Steven C. Bartling ,  Sudhanshu Khanna

IPC: H03K3/037

CPC classification number: H03K3/356008

Abstract: In an embodiment of the invention, a dual-port negative level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口负电平敏感预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变低，CLKZ变为高电平，预置控制信号PRE为低电平，保持控制信号RET为低电平时，数据通过时钟反相器进行时钟控制。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET和RETN，预置控制信号PRE和控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，PRE，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号RET和RETN确定数据是否存储在双端口锁存器中。

公开(公告)号：US20150054544A1

公开(公告)日：2015-02-26

申请号：US14080092

申请日：2013-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven C. Bartling ,  Sudhanshu Khanna

IPC: H03K19/173

CPC classification number: H03K19/1735 ,  H03K3/356008

Abstract: In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的实施例中，双端口正电平敏感预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，预置控制信号PRE为低电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET和RETN，预置控制信号PRE和控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，PRE，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号RET和RETN确定数据是否存储在双端口锁存器中。

公开(公告)号：US20140347114A1

公开(公告)日：2014-11-27

申请号：US14457310

申请日：2014-08-12

Applicant: Texas Instruments Incorporated

Inventor： Steven Bartling ,  Sudhanshu Khanna

IPC: H03K3/012 ,  H03K3/289

CPC classification number: H03K3/012 ,  H03K3/289 ,  H03K3/35625

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract translation: 在本发明的实施例中，触发器电路包含2输入多路复用器，主锁存器，传输门和从锁存器。 复用器的扫描使能控制信号SE和SEN确定数据还是扫描数据被输入到主锁存器。 时钟信号CLK和CLKN以及保持控制信号RET和RETN确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号CLK和CLN，保持控制信号RET和RETN，从控制信号SS和SSN。 信号CLK，CLKN，RET，RETN，SS和SSN确定主锁存器或第二数据位D2的输出是否被锁存在从锁存器中。 在保持模式期间，控制信号RET和RETN确定数据是否存储在从锁存器中。

公开(公告)号：US08854858B2

公开(公告)日：2014-10-07

申请号：US13753819

申请日：2013-01-30

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C11/22 ,  H03K3/02

CPC classification number: H03K3/02 ,  G11C11/2275 ,  G11C11/419 ,  G11C14/0072 ,  H03K3/356104

Abstract: A system on chip (SoC) includes one or more core logic blocks that are configured to operate on a lower supply voltage and a memory array configured to operate on a higher supply voltage. Each bitcell in the memory has two ferroelectric capacitors connected in series between a first plate line and a second plate line to form a node Q. A data bit voltage is transferred to the node Q by activating a write driver to provide the data bit voltage responsive to the lower supply voltage. The data bit voltage is boosted on the node Q by activating a sense amp coupled to node Q of the selected bit cell, such that the sense amp senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage.

Abstract translation: 片上系统（SoC）包括配置为在较低电源电压下操作的一个或多个核心逻辑块和配置为在较高电源电压下工作的存储器阵列。 存储器中的每个位单元具有串联连接在第一板线和第二板线之间以形成节点Q的两个铁电电容器。通过激活写驱动器将数据位电压传送到节点Q以提供数据位电压响应 到较低的电源电压。 通过激活耦合到所选位单元的节点Q的读出放大器，在节点Q上升高数据位电压，使得感测放大器感测节点Q上的数据位电压，并且响应于增加节点上的数据位电压 Q到更高的电源电压。

公开(公告)号：US08817520B2

公开(公告)日：2014-08-26

申请号：US13753814

申请日：2013-01-30

Applicant: Texas Instruments Incorporated

Inventor： Sudhanshu Khanna ,  Steven Craig Bartling

IPC: G11C11/22

CPC classification number: G11C11/221

Abstract: A system on chip (SoC) provides a memory array of self referencing nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit coupled to the node Q. A first read capacitor is coupled to the bit line via a transfer device controlled by a first control signal. A second read capacitor coupled to the bit line via another transfer device controlled by a second control signal. A sense amp is coupled between the first read capacitor and the second read capacitor.

Abstract translation: 片上系统（SoC）提供了自参考非易失性位单元的存储器阵列。 每个位单元包括在第一板线和第二板线之间串联连接的两个铁电电容器，使得在两个铁电电容器之间形成节点Q。 第一板线和第二板线配置成在位单元未被访问时提供大致等于第一电压的电压。 耦合到节点Q的钳位电路。第一读取电容器经由由第一控制信号控制的传输装置耦合到位线。 通过由第二控制信号控制的另一转移装置耦合到位线的第二读电容器。 感测放大器耦合在第一读取电容器和第二读取电容器之间。

公开(公告)号：US20140075091A1

公开(公告)日：2014-03-13

申请号：US13770583

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F3/06

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processing device handles two or more operating threads. A non-volatile logic controller stores first program data from a first program in a first set of non-volatile logic element arrays and second program data from a second program in a second set of non-volatile logic element arrays. The first program and the second program can correspond to distinct executing threads, and the storage can be completed in response to receiving a stimulus regarding an interrupt for the computing device apparatus or in response to a power supply quality problem for the computing device apparatus. When the device needs to switch between processing threads, the non-volatile logic controller restores the first program data or the second program data from the non-volatile logic element arrays in response to receiving a stimulus regarding whether the first program or the second program is to be executed by the computing device apparatus.

Abstract translation: 处理设备处理两个或多个操作线程。 非易失性逻辑控制器将第一程序中的第一程序数据存储在第一组非易失性逻辑单元阵列中的第一程序数据和来自第二组非易失性逻辑单元阵列中的第二程序的第二程序数据中。 第一程序和第二程序可以对应于不同的执行线程，并且响应于接收到关于计算设备装置的中断的刺激或响应于计算设备装置的电源质量问题，可以完成存储。 当设备需要在处理线程之间切换时，非易失性逻辑控制器响应于接收关于第一程序或第二程序是否为...的刺激而从非易失性逻辑单元阵列恢复第一程序数据或第二程序数据 由计算设备设备执行。

公开(公告)号：US20140075090A1

公开(公告)日：2014-03-13

申请号：US13770399

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F12/02

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.

Abstract translation: 处理装置包括具有两个或多个非易失性逻辑元件阵列的多个非易失性逻辑元件阵列域，以存储存储在多个易失性存储元件中的处理装置的机器状态。 读取配置位以指示首先启用哪些非易失性逻辑单元阵列域并且响应于进入唤醒或备份模式来引导第一启用的非易失性逻辑单元阵列域被还原或备份的顺序。 可以读取配置位以指导第一使能的非易失性逻辑单元阵列域中的各个非易失性逻辑单元阵列如何恢复或备份的顺序和并行性。 可以通过来自多个非易失性逻辑单元阵列域的第一使能的非易失性阵列的指令来控制恢复或备份的顺序。