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    Wideband low distortion power amplifier
    21.
    发明授权
    Wideband low distortion power amplifier 有权

    公开(公告)号：US10291270B2

    公开(公告)日：2019-05-14

    申请号：US16148891

    申请日：2018-10-01

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sudipto Chakraborty

    IPC: H04B1/04 ,  H03F3/24

    Abstract: A circuit and apparatus for filtering harmful harmonics is disclosed. The circuit and apparatus include a power amplifier core that uses equally sized inverter based amplifiers. The amplifier core cells provide uniform load to all phases of a fundamental frequency to cancel all harmonics at an output. The power amplifier stages are driven into nonlinearity, and the combination of harmonics is performed at the output by varying series connected capacitors. The harmonic combination is performed at the output, leaving no further scope of nonlinearity in the signal chain.

    Differential odd integer divider
    22.
    发明授权
    Differential odd integer divider 有权

    公开(公告)号：US09948309B2

    公开(公告)日：2018-04-17

    申请号：US14541578

    申请日：2014-11-14

    Applicant: Texas Instruments Incorporated

    Inventor： Sudipto Chakraborty

    IPC: H03K23/00 ,  H03K23/70 ,  H03K3/012

    CPC classification number: H03K23/70 ,  H03K3/012

    Abstract: A differential odd integer divider provides low power and compact sub-harmonics of an applied square or sinusoidal clock signal with self-aligned 50% duty cycle. The odd integer divider circuit includes a set of low power delay cells connected in a ring fashion. Each delay cell includes two differential dual port inputs connected to the gates of MOS transistors. For instance, these odd integer dividers include a series of low power latch circuits that are custom configured for minimum headroom and low power consumption. These output phasors can then be combined with an appropriate weight factor to provide a near-sinusoidal waveshape from the input square waveshape. Intrinsic 50% duty cycle maybe shortened or stretched by using combinatorial logic circuits.

    System and method for reconfigurable phase shifter and mixer
    26.
    发明授权
    System and method for reconfigurable phase shifter and mixer 有权

    公开(公告)号：US09602054B2

    公开(公告)日：2017-03-21

    申请号：US14930210

    申请日：2015-11-02

    Applicant: Texas Instruments Incorporated

    Inventor： Sudipto Chakraborty

    IPC: H03H11/16 ,  H03D7/14 ,  H03H11/20 ,  H03K5/01 ,  H03K5/00

    CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03H11/20 ,  H03K5/01 ,  H03K2005/00286

    Abstract: An analog circuit for generating a periodic signal at a selected phase, including one or more phase interpolators that receive orthogonal differential RF signals and a pair of differential gain signals. The differential in-phase RF signal is applied at respective gates of tail transistors, and a first differential gain signal is applied across gates of a transistor pair coupled to each of the tail transistors. The quadrature-phase RF signal and a second differential gain signal is similarly applied to another quad of transistors (i.e., pair of transistor pairs) and associated tail transistors. A load connected to the one transistor in each pair receives the output signal, at a phase corresponding to a ratio of the first and second gain signals. The gain signals may be DC or AC, which allows configuration of the circuit as a phase shifter or an upconversion mixer, and the load may be presented by a transform in which the phase also depends on the relative coupling from the in-phase and quadrature-phase sides of the phase interpolator.

    Concurrent, reconfigurable, low power harmonic wake-up and main radio receiver
    27.
    发明授权
    Concurrent, reconfigurable, low power harmonic wake-up and main radio receiver 有权
    并发，可重配置，低功率谐波唤醒和主要无线电接收器

    公开(公告)号：US09510288B1

    公开(公告)日：2016-11-29

    申请号：US14819966

    申请日：2015-08-06

    Applicant: Texas Instruments Incorporated

    Inventor： Sudipto Chakraborty

    IPC: H04L27/06 ,  H04W52/02

    CPC classification number: H04W52/0229 ,  H04W52/0274 ,  H04W52/028 ,  Y02D70/00

    Abstract: A wireless receiver includes a receiver front-end where the input of the LNA and the mixer have separate main radio and wake-up modes, where same DC voltage is used at the input of the LNA, and the input of the baseband filter. When the receiver switches between the wake-up and main radio mode, wake-up current usage is reduced due to near zero latency in programming bias voltages from the power management unit. The receiving circuitry can one or both of selectively change a signal processing path for the receiving circuitry or selectively configure signal processing circuits of the receiving circuitry when switching between the wake-up mode configuration and the main radio mode configuration. The programming and configurations are dependent on the dynamic range and modulation techniques and requires near zero area overhead compared with the main radio receiver.

    Abstract translation: 无线接收机包括接收器前端，其中LNA和混频器的输入具有分离的主无线电和唤醒模式，其中在LNA的输入处使用相同的DC电压和基带滤波器的输入。 当接收器在唤醒和主无线电模式之间切换时，由于来自电源管理单元的编程偏置电压接近零延迟，所以唤醒电流的使用会降低。 接收电路可以选择性地改变用于接收电路的信号处理路径中的一个或两者，或者当在唤醒模式配置和主无线电模式配置之间切换时，选择性地配置接收电路的信号处理电路。 编程和配置取决于动态范围和调制技术，并且与主无线电接收机相比需要接近零的开销。

    Systems and methods of polyphase generation
    28.
    发明授权
    Systems and methods of polyphase generation 有权
    多相生成的系统和方法

    公开(公告)号：US09438456B1

    公开(公告)日：2016-09-06

    申请号：US14887566

    申请日：2015-10-20

    Applicant: Texas Instruments Incorporated

    Inventor： Sudipto Chakraborty ,  Swaminathan Sankaran

    IPC: H04L27/20

    CPC classification number: H04L27/2067 ,  H04L2027/0018 ,  H04L2027/0051 ,  H04L2027/0059

    Abstract: Example embodiments of the systems and methods of polyphase generation involve quadrature generation in high frequency digital transceivers. An oscillation signal is received and converted to complex variables with lead and lag phase rotation while performing compensation and calibration due to non-idealities of the in-phase and quadrature phase component parts. In addition to orthagonalizating, the quadrature generator also provides signal amplification and filtering. The quadrature phase generation scheme may be extended to odd harmonics of the fundamental frequency at the input.

    Abstract translation: 多相生成的系统和方法的示例实施例涉及高频数字收发器中的正交生成。 由于同相和正交相位分量的非理想性，在进行补偿和校准的同时，接收振荡信号并将其转换为带有前导和滞后相位旋转的复数变量。 除了对角化之外，正交发生器还提供信号放大和滤波。 正交相位生成方案可以扩展到输入端的基频的奇次谐波。

    Low Power Harmonic Wake Up Radio
    29.
    发明申请
    Low Power Harmonic Wake Up Radio 有权
    低功率谐波唤醒无线电

    公开(公告)号：US20160198409A1

    公开(公告)日：2016-07-07

    申请号：US14588629

    申请日：2015-01-02

    Applicant: Texas Instruments Incorporated

    Inventor： Sudipto Chakraborty

    IPC: H04W52/02 ,  H04B1/16

    CPC classification number: H04W52/0229 ,  Y02D70/00

    Abstract: A wireless receiver includes a receiver mixer having at least two sets of switches connected to selectively pass a portion of a received RF signal to the mixer's output. Different sets of the switches are activated by different phases of a local oscillator to effect passing of different phases of the RF signal to the output. These outputs are combined in various ways to obtain operation of the main receiver and the wake up receiver modes at harmonically related carrier frequencies with as low as possible subharmonic multi-phase clock generation network. This can be used to detect a wake up signal with a very fast response time, minimal area overhead, minimal power usage, and equal loading to the local oscillator network providing the phases to the mixer to maintain excellent phase balance and precise harmonic selectivity.

    Abstract translation: 无线接收机包括具有至少两组开关的接收机混频器，所述至少两组开关被连接以选择性地将接收到的RF信号的一部分传送到混频器的输出端。 不同组的开关由本地振荡器的不同相位激活，以实现将RF信号的不同相位传递到输出端。 这些输出以各种方式组合以获得具有尽可能低的次谐波多相时钟生成网络的谐波相关载波频率下的主接收机和唤醒接收机模式的操作。 这可以用于以非常快的响应时间，最小的面积开销，最小的功率使用率以及与本地振荡器网络相等的负载来检测唤醒信号，从而为混频器提供相位以保持良好的相位平衡和精确的谐波选择性。

    Built in self test and method for RF transceiver systems
    30.
    发明授权
    Built in self test and method for RF transceiver systems 有权
    内置射频收发系统的自检和方法

    公开(公告)号：US09385774B2

    公开(公告)日：2016-07-05

    申请号：US14821194

    申请日：2015-08-07

    Applicant: Texas Instruments Incorporated

    Inventor： Sudipto Chakraborty

    IPC: H04B1/40 ,  H04B17/00 ,  H04W52/02

    CPC classification number: H04B1/40 ,  H04W52/02 ,  H04W52/0261 ,  Y02D70/00 ,  Y02D70/144 ,  Y02D70/40

    Abstract: Integrated circuit transceiver circuitry (2) includes a first resonant circuit (3A) coupled to a narrowband interface (6,7A,7B,21) between a first amplifier (3,20) and an interfacing circuit (4,8,9,44), including a programmable first reactive element (C) and a second reactive element (L). Amplitude sensing circuitry (42) senses a maximum amplitude of an in-phase signal (I) or a quadrature-phase signal (Q). An on-chip first tone generation circuit (38,38A,38B,38C) generates tones for injection into the in-phase signal and the quadrature-phase signal and operates in response to frequency scanning circuitry (30) and the amplitude sensing circuitry to adjust the first reactive element (C) to calibrate the first resonant circuit to a desired resonant frequency by selectively coupling reactive sub-elements (1, 2, 4, 8 . . . ×Cv) into the first reactive element (C).

    Abstract translation: 集成电路收发器电路（2）包括耦合到第一放大器（3,20）和接口电路（4,8,9,44）之间的窄带接口（6,7A，7B，21）的第一谐振电路（3A） ），包括可编程的第一电抗元件（C）和第二电抗元件（L）。 幅度感测电路（42）感测同相信号（I）或正交相位信号（Q）的最大振幅。 片上第一音调产生电路（38,38A，38B，38C）产生用于注入到同相信号和正交相位信号中的音调，并响应于频率扫描电路（30）和振幅检测电路 通过选择性地将反应子元件（1,2,4,8 ...×Cv）耦合到第一电抗元件（C）中，来调节第一电抗元件（C）以将第一谐振电路校准到期望的谐振频率。

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