公开(公告)号：US11791198B2

公开(公告)日：2023-10-17

申请号：US17695119

申请日：2022-03-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Ya ping Chen ,  Fei Ma ,  Yunlong Liu ,  Sunglyong Kim

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/76235 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/324 ,  H01L21/763 ,  H01L21/76283 ,  H01L21/76286 ,  H01L29/66666

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

公开(公告)号：US20230223395A1

公开(公告)日：2023-07-13

申请号：US17854998

申请日：2022-06-30

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Sudheer Prasad ,  Sreeram N. S. ,  Sandip Lashkare ,  Christopher Kocon

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0292

Abstract: Electrostatic discharge (ESD) protection devices with high current capability are described. The ESD protection device may include a pair of bidirectional diodes (first and second bidirectional diodes) connected in series. Each of the bidirectional diodes includes a low capacitance (LC) diode and a bypass diode connected in parallel. During ESD events, current flows through the LC diode of the first bidirectional diode and the bypass diode of the second bidirectional diode. Particular arrangements of the LC diodes and the bypass diodes are devised to facilitate uniform distribution of the current throughout an area occupied by the ESD protection device.

公开(公告)号：US20230223393A1

公开(公告)日：2023-07-13

申请号：US17855105

申请日：2022-06-30

Applicant: Texas Instruments Incorporated

Inventor： Christopher Kocon ,  Sunglyong Kim ,  Sreeram N. S. ,  Sudheer Prasad ,  Sandip Lashkare

IPC: H01L27/02

CPC classification number: H01L27/0248

Abstract: Semiconductor devices with high current capability for ESD or surge protection are described. The semiconductor device includes multiple n-type semiconductor regions in a p-type semiconductor layer. Each of the n-type semiconductor regions may have a footprint with a circular, oval, or obround shape. Moreover, a boundary of the footprint may be spaced apart from an isolation structure that surrounds the p-type semiconductor layer. The n-type semiconductor regions may be coupled to a terminal through individual groups of contacts that are connected to the n-type semiconductor regions, respectively. Additionally, or alternatively, the p-type semiconductor layer surrounded by the isolation structure may not include any re-entrant corner.

公开(公告)号：US11456381B2

公开(公告)日：2022-09-27

申请号：US17123835

申请日：2020-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Meng-Chia Lee ,  Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: Described examples include an integrated circuit having a semiconductor substrate. The integrated circuit has a transistor that includes a buried layer having within the substrate, the buried layer defining a drift region between the buried layer and the top surface and a body region in the substrate extending from the buried layer to the surface of the substrate. The transistor also having a source formed in the body region, a drain extending from the buried layer to the surface of the substrate, a drift well extending from the buried layer toward the top surface and extending from the body region to the drain, a drift surface layer located between the drift well and the top, and a gate proximate to the surface of the substrate at the body region.

公开(公告)号：US20220190158A1

公开(公告)日：2022-06-16

申请号：US17123835

申请日：2020-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Meng-Chia Lee ,  Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: Described examples include an integrated circuit having a semiconductor substrate. The integrated circuit has a transistor that includes a buried layer having within the substrate, the buried layer defining a drift region between the buried layer and the top surface and a body region in the substrate extending from the buried layer to the surface of the substrate. The transistor also having a source formed in the body region, a drain extending from the buried layer to the surface of the substrate, a drift well extending from the buried layer toward the top surface and extending from the body region to the drain, a drift surface layer located between the drift well and the top, and a gate proximate to the surface of the substrate at the body region.

公开(公告)号：US11322610B2

公开(公告)日：2022-05-03

申请号：US16776544

申请日：2020-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/78 ,  H01L21/28 ,  H03K17/687 ,  H01L29/10 ,  H01L21/761 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L27/07 ,  H01L29/08 ,  H03K17/12 ,  H01L29/423

Abstract: A device includes a laterally diffused MOSFET, which in turn includes n-type source and drain regions in a p-type semiconductor substrate. A gate electrode is located over the semiconductor substrate between the source region and the drain region. An isolation region is laterally spaced apart from the source region, and is bounded by an n-type buried layer and an n-type well region that reaches from a surface of the substrate to the buried layer. A p-type doped region and an n-type doped region are disposed within the isolation region, the p-type doped region and the n-type doped region forming a diode. A first conductive path connects the n-type doped region to the source region, and a second conductive path connects the p-type doped region to the gate electrode.

公开(公告)号：US11302568B2

公开(公告)日：2022-04-12

申请号：US16546499

申请日：2019-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Ya ping Chen ,  Fei Ma ,  Yunlong Liu ,  Sunglyong Kim

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/308 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

公开(公告)号：US11239318B2

公开(公告)日：2022-02-01

申请号：US16846754

申请日：2020-04-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor device includes a MOS transistor located within a semiconductor substrate of a first conductivity type. The transistor includes a body well located between a drain well and a substrate contact well. A buried voltage blocking region of a second conductivity type is located within the substrate and is connected to the body well. The buried voltage blocking region extends toward the substrate contact well, with an unmodified portion of the substrate remaining between the voltage blocking region and the substrate contact well.

公开(公告)号：US10950720B2

公开(公告)日：2021-03-16

申请号：US15790780

申请日：2017-10-23

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  David LaFonteese

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H02H9/04 ,  H01L29/423 ,  H03K19/0185 ,  H01L29/10 ,  H01L29/40

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

公开(公告)号：US20240113217A1

公开(公告)日：2024-04-04

申请号：US17958205

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Thomas Grebs ,  Yunlong Liu ,  Sunglyong Kim ,  Lindong Li ,  Peng Li ,  Seetharaman Sridhar ,  Yeguang Zhang ,  Sheng pin Yang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/823437 ,  H01L27/092 ,  H01L29/42368

Abstract: An integrated circuit includes first and second trenches in a semiconductor substrate and a semiconductor mesa between the first and second trenches. A source region having a first conductivity type and a body region having an opposite second conductivity type are located within the semiconductor mesa. A trench shield is located within the first trench, and a gate electrode is over the trench shield between first and second sidewalls of the first trench. A gate dielectric is on a sidewall of the first trench between the gate electrode and the body region, and a pre-metal dielectric (PMD) layer is over the gate electrode. A gate contact through the PMD layer touches the gate electrode between the first and second sidewalls, and a trench shield contact through the PMD layer touches the trench shield between the first and second sidewalls.