公开(公告)号：US20050206018A1

公开(公告)日：2005-09-22

申请号：US11129710

申请日：2005-05-13

申请人： Tadahiro Ohmi ,  Takashi Imaoka ,  Hisayuki Shimada ,  Nobuhiro Konishi ,  Mizuho Morita ,  Takeo Yamashita ,  Tadashi Shibata ,  Hidetoshi Wakamatsu ,  Jinzo Watanabe ,  Shintaro Aoyama ,  Masakazu Nakamura

发明人： Tadahiro Ohmi ,  Takashi Imaoka ,  Hisayuki Shimada ,  Nobuhiro Konishi ,  Mizuho Morita ,  Takeo Yamashita ,  Tadashi Shibata ,  Hidetoshi Wakamatsu ,  Jinzo Watanabe ,  Shintaro Aoyama ,  Masakazu Nakamura

IPC分类号： B01J19/08 ,  C23C8/10 ,  C23C8/36 ,  C23C14/02 ,  C23C14/48 ,  C23C16/02 ,  C23C16/44 ,  C30B23/02 ,  C30B25/02 ,  G01N23/00 ,  H01L21/66

CPC分类号： C30B23/02 ,  C23C8/10 ,  C23C8/36 ,  C23C14/022 ,  C23C14/48 ,  C23C16/02 ,  C23C16/4401 ,  C30B25/02 ,  C30B29/16 ,  Y10S438/903

摘要： Vacuum processing equipment capable of preventing particles from sticking to objects to be processed in vacuum vessels. The vacuum equipment comprises a series of vacuum vessels separated by doors, and the pressure in the vessels are reducible respectively. The vessels are so configured that objects to be processed are moveable among them and there is provided light projection means for projecting ultra rays on gases introduced to at least of the vessels.

摘要翻译： 真空处理设备能够防止颗粒粘附在真空容器中被处理物体。 真空设备包括一系列由门隔开的真空容器，容器中的压力分别可减少。 容器被配置成使待处理的物体在它们之间是可移动的，并且设置有用于将超光线投射到至少导入到容器中的气体的光投射装置。

公开(公告)号：US06704757B1

公开(公告)日：2004-03-09

申请号：US09673516

申请日：2001-01-02

申请人： Tadahiro Ohmi ,  Tadashi Shibata ,  Akira Nakada ,  Tatsuro Morimoto ,  Takahisa Nitta

发明人： Tadahiro Ohmi ,  Tadashi Shibata ,  Akira Nakada ,  Tatsuro Morimoto ,  Takahisa Nitta

IPC分类号： G06J100

CPC分类号： G06N3/063 ,  G06N3/0635

摘要： A semiconductor arithmetic unit which realizes a maximum or minimum value retrieval operation at high speed and with a high degree of accuracy used in a vector quantization processor is composed of a binary-multivalue-analog merged operation processing circuit. A multi-loop circuit includes an amplifying circuit group composed of a plurality of sets of first amplifiers with a floating gate to which first electrodes and a single second electrode are capacitively coupled with a predetermined ratio, a logical operation circuit to which output signals of the amplifying circuit group are inputted and which outputs a logical 0 or 1, and a second amplifying circuit to which an output signal of the logical operation circuit is inputted and whose output is distributed to all of the second electrodes of the amplifying circuit group. The second amplifying circuit includes an adjusting circuit which adjusts an output current driving ability and a controlling circuit which controls the adjustment with a predetermined regulation. The adjustment of the controlling circuit is executed according to variation of the output of the logical operation circuit.

摘要翻译： 实现在矢量量化处理器中使用的高速度和高精度的最大值或最小值检索操作的半导体运算单元由二进制多值模拟合并运算处理电路构成。 多回路电路包括由具有浮置栅极的多组第一放大器组成的放大电路组，第一电极和单个第二电极以预定比率电容耦合到该第一放大器;逻辑运算电路， 输入逻辑0或1的放大电路组，输入逻辑运算电路的输出信号并将其输出分配给放大电路组的所有第二电极的第二放大电路。 第二放大电路包括调节输出电流驱动能力的调节电路和控制电路，控制电路以预定的调节进行调节。 控制电路的调整根据逻辑运算电路的输出的变化进行。

公开(公告)号：US6127857A

公开(公告)日：2000-10-03

申请号：US110011

申请日：1998-07-02

申请人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

发明人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

IPC分类号： H01L27/092 ,  H03K19/003 ,  H03K19/00

CPC分类号： H03K19/00315 ,  H01L27/092

摘要： In order to prevent an output offset voltage from occurring because of a relative difference of threshold voltage Vth between NMOS and PMOS in transmission of dc voltage, a semiconductor integrated circuit is constructed in a circuit configuration comprising a first depletion-mode N-channel MOS transistor and a first depletion-mode P-channel MOS transistor, a gate of each transistor being connected to an input terminal and a source of each transistor being connected to an output terminal, a second depletion-mode N-channel MOS transistor having W/L equal to that of the first depletion-mode P-channel MOS transistor, a drain of the transistor being connected to the output terminal and a gate and a source of the transistor being connected both to a lower-voltage-side power supply, and a second depletion-mode P-channel MOS transistor having W/L equal to that of the first depletion-mode P-channel MOS transistor, a drain of the transistor being connected to the output terminal and a gate and a source of the transistor being connected both to a higher-voltage-side power supply.

摘要翻译： 为了防止由于在直流电压传输期间NMOS和PMOS之间的阈值电压Vth的相对差异而产生输出偏移电压，半导体集成电路被构造成包括第一耗尽型N沟道MOS晶体管 和第一耗尽型P沟道MOS晶体管，每个晶体管的栅极连接到输入端子，每个晶体管的源极连接到输出端子，具有W / L的第二耗尽型N沟道MOS晶体管 等于第一耗尽型P沟道MOS晶体管的漏极，晶体管的漏极连接到输出端子，并且晶体管的栅极和源极都连接到低压侧电源，以及 具有与第一耗尽型P沟道MOS晶体管相等的W / L的第二耗尽型P沟道MOS晶体管，晶体管的漏极连接到输出端子，栅极和 晶体管的源极连接到较高电压侧电源。

公开(公告)号：US5973535A

公开(公告)日：1999-10-26

申请号：US666506

申请日：1996-10-15

申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Takeo Yamashita

发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Takeo Yamashita

IPC分类号： G06F3/05 ,  G06F15/18 ,  G06G7/60 ,  G06N3/06 ,  G06N3/063 ,  G11C27/00 ,  H01L21/8234 ,  H01L27/088 ,  H03K3/3568 ,  H03K19/20 ,  H03M1/12 ,  H03M1/36 ,  H03M1/80 ,  H03K5/08

CPC分类号： G06N3/0635 ,  G11C27/005 ,  H03K3/3568 ,  H03M1/36 ,  H03M1/802

摘要： A simple semiconductor circuit by which analog data or multilevel data can be fetched and stored. The circuit receives a first signal and converts the first signal into a second signal composed of multilevel. The second signal is fed back to the circuit. The circuit is constituted of a first circuit which converts the first signal into a signal group composed of multiple quantized signals and second circuit which converts the signal group into the second signal. In addition, the first or/and second circuits are constituted of one or more neuron MOS transistors.

摘要翻译： PCT No.PCT / JP94 / 02258 Sec。 371日期：1996年6月28日 102（e）日期1996年6月28日PCT 1994年12月27日PCT PCT。 WO95 / 18488 PCT公开 日期1995年7月6日简单的半导体电路可以获取和存储模拟数据或多级数据。 电路接收第一信号并将第一信号转换成由多电平组成的第二信号。 第二个信号被反馈回电路。 电路由将第一信号转换为由多个量化信号组成的信号组的第一电路和将信号组转换为第二信号的第二电路构成。 此外，第一或/和第二电路由一个或多个神经元MOS晶体管构成。

公开(公告)号：US5959484A

公开(公告)日：1999-09-28

申请号：US807374

申请日：1997-02-27

申请人： Tadahiro Ohmi ,  Tadashi Shibata ,  Hiroaki Terada ,  Koji Kotani

发明人： Tadahiro Ohmi ,  Tadashi Shibata ,  Hiroaki Terada ,  Koji Kotani

IPC分类号： G06G7/60 ,  H01L21/8234 ,  H01L27/088 ,  H03K3/356 ,  H03K19/08 ,  H03K19/20

CPC分类号： H03K19/0813

摘要： A feedback circuit is provided which is capable of realizing handshake functions, flip flop functions, and other functions using a smaller number of elements and chip surface. The threshold circuit is provided with an electrode which is electrically floating and a plurality of input electrodes which are connected with the floating electrode via capacity elements, and the circuit has a mechanism for essentially determining the potential of the floating electrode by means of the potentials applied to the input electrodes, and the output of the circuit is determined by the potential of the floating gate; the output of the threshold circuit is connected to at least one of the plurality of input electrodes, either directly, or via at least one circuit of some type.

摘要翻译： 提供了一种反馈电路，其能够使用较少数量的元件和芯片表面来实现握手功能，触发器功能和其他功能。 阈值电路设置有电浮动的电极和通过电容元件与浮动电极连接的多个输入电极，并且电路具有用于通过施加的电位基本上确定浮置电极的电位的机构 到输入电极，并且电路的输出由浮栅的电位确定; 阈值电路的输出直接或经由某种类型的至少一个电路连接到多个输入电极中的至少一个。

公开(公告)号：US5956434A

公开(公告)日：1999-09-21

申请号：US930548

申请日：1997-11-07

申请人： Tadashi Shibata ,  Tadahiro Ohmi

发明人： Tadashi Shibata ,  Tadahiro Ohmi

IPC分类号： G06G7/26 ,  G06K15/316 ,  G06K9/64

CPC分类号： G06G7/26

摘要： The present invention has as an object thereof to provide a semiconductor operational circuit which is capable of instantaneously processing in parallel a large quantity of information. The semiconductor operational circuit of the present invention which executes a predetermined operation with respect to a first signal train of signals A.sub.1, A.sub.2, . . . , A.sub.N-1, A.sub.N (where N is a positive integer) of N signals numbered from 1 to N, and a second signal train of signals B.sub.1, B.sub.2, . . . , B.sub.M-1, B.sub.M (where M is a positive integer) of M signals numbered from 1 to M, comprising a plurality of first operational circuits for executing a predetermined operation with respect to A.sub.i, and B.sub.i+n (where i is a positive integer and n is a positive or negative integer and 1.ltoreq.i.ltoreq.n and 1.ltoreq.i+n.ltoreq.M) and generating an output signal C.sub.i,n, at least one second operational circuit for generating the sum S.sub.n of a part or the whole of output signals of the first operational circuits with respect to a predetermined value of n, where i has differing values, or for generating a predetermined signal T.sub.n, determined by the sum S.sub.n, and a third operational circuit for finding the value of S.sub.n or T.sub.n, with respect to a plurality of different n values and for determining the n value for which the maximum or minimum value of S.sub.n or T.sub.n is given.

摘要翻译： PCT No.PCT / JP96 / 00885 Sec。 371日期：1997年11月7日 102（e）日期1997年11月7日PCT 1996年4月1日PCT PCT。 WO96 / 30854 PCT出版物 日期：1996年10月3日本发明的目的在于提供能够并行地并行处理大量信息的半导体运算电路。 本发明的半导体运算电路相对于信号A1，A2的第一信号序列执行预定的操作。 。 。 ，AN-1，AN（其中N是正整数）从1到N编号的N个信号和信号B1，B2的第二信号串。 。 。 ，BM-1，BM（其中M为正整数），编号为1至M的M个信号，包括用于执行关于Ai的预定操作的多个第一操作电路，以及Bi + n（其中i为正 整数，n是正整数和负整数，并且1 = i i = 1，并且产生输出信号Ci，n，至少一个第二运算电路，用于产生 相对于预定值n的第一运算电路的输出信号的一部分或整体的总和Sn，其中i具有不同的值，或者用于产生由该和Sn确定的预定信号Tn，以及第三运算电路 用于找到Sn或Tn的值，相对于多个不同的n值，并且用于确定给出Sn或Tn的最大值或最小值的n值。

公开(公告)号：US5923779A

公开(公告)日：1999-07-13

申请号：US719915

申请日：1996-09-25

申请人： Tadahiro Ohmi ,  Tadashi Shibata

发明人： Tadahiro Ohmi ,  Tadashi Shibata

IPC分类号： G06G7/19 ,  G06G7/12 ,  G06K9/00 ,  G06K9/66 ,  G06K9/46

CPC分类号： G06K9/00986 ,  G06K9/00221 ,  G06K9/4604

摘要： The present invention has as an object thereof to provide an intelligent electronical system which conducts the real-time recognition of real world data and makes decisions with respect to the data; that is to say, a computing circuit having an instantaneous recognition function and instantaneous recognition method. The invention relates to a computing circuit which selects predetermined codes with respect to a group of inputted signals comprising a plurality of analog signals, which is provided with: a mechanism whereby the group of inputted signals is converted to a group of input variables comprising a number of analog variables or multilevel variables which is smaller in number than analog signals, a memory circuit which stores a plurality of data comprising groups of a plurality of analog or multilevel variables determined in advance, a circuit which conducts a predetermined comparison operation between the group of input variables and a plurality of data stored in the memory circuit simultaneously and in parallel, and a mechanism for selecting at least one code corresponding to data which fit predetermined conditions, as a result of the comparison operation.

摘要翻译： 本发明的目的是提供一种智能电子系统，其对现实世界数据进行实时识别并对数据作出决定; 也就是说，具有瞬时识别功能和瞬时识别方法的计算电路。 本发明涉及一种计算电路，其针对包括多个模拟信号的一组输入信号选择预定代码，该组包括：一组机构，其中输入信号组被转换成包括一组数字的输入变量组 模拟量变量或多级变量，其数量小于模拟信号;存储器电路，存储包括预先确定的多个模拟或多级变量的组的多个数据;电路，其进行预定比较操作; 作为比较操作的结果，同时并行地存储在存储器电路中的输入变量和多个数据以及用于选择与适合预定条件的数据相对应的至少一个代码的机构。

公开(公告)号：US5854116A

公开(公告)日：1998-12-29

申请号：US422640

申请日：1995-04-14

申请人： Tadahiro Ohmi ,  Tadashi Shibata ,  Masaru Umeda

发明人： Tadahiro Ohmi ,  Tadashi Shibata ,  Masaru Umeda

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/20

CPC分类号： H01L21/2855 ,  H01L21/76838

摘要： The present invention relates to a semiconductor apparatus adapted to a ultrahigh density integration process. A semiconductor apparatus of the present invention is characterized by including a high concentration impurity layer with the same type of conductivity as that of a semiconductor wafer provided on the back of the semiconductor wafer, and at least one layer of a low resistance electrode provided on said high concentration impurity layer.

摘要翻译： 本发明涉及适用于超高密度集成处理的半导体装置。 本发明的半导体装置的特征在于包括具有与设置在半导体晶片的背面上的半导体晶片相同类型的导电性的高浓度杂质层，以及至少一层设置在所述半导体晶片上的低电阻电极 高浓度杂质层。

公开(公告)号：US5719520A

公开(公告)日：1998-02-17

申请号：US537729

申请日：1995-10-13

申请人： Rita Wai-Chi Au ,  Tadashi Shibata ,  Tadahiro Ohmi

发明人： Rita Wai-Chi Au ,  Tadashi Shibata ,  Tadahiro Ohmi

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C27/00 ,  H03K17/687

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5692 ,  G11C27/005 ,  G11C16/08 ,  G11C2211/5611 ,  G11C8/14

摘要： A semiconductor circuit which realizes a read-only memory cell having zero stand-by power consumption and capable of non-volatile storage of multiple-valued or analog data. This semiconductor device is comprises of at least a single-channel or p-channel MOS transistor in a source-follower circuit configuration. The input of this source-follower circuit is a floating gate which is capacitively coupled to multiple control gates. The voltages applied to the control gates and the coupling ratios of the control gates determine the potential of the floating gate. When a voltage supply is applied to the drain electrode of the source-follower circuit, the source-electrode potential will nearly equal the floating gate potential.

摘要翻译： PCT No.PCT / JP94 / 00217 Sec。 371 1995年10月13日第 102（e）日期1995年10月13日PCT 1994年2月15日PCT PCT。 公开号WO95 / 22145 日期1995年8月17日一种半导体电路，其实现具有零待机功耗的只读存储器单元，并且能够进行多值或模拟数据的非易失性存储。 该半导体器件由源极跟随器电路配置中的至少一个单沟道或p沟道MOS晶体管构成。 该源跟随器电路的输入是浮动栅极，其电容耦合到多个控制栅极。 施加到控制栅极的电压和控制栅极的耦合比决定了浮动栅极的电位。 当源极跟随器电路的漏电极施加电压源时，源极电位将几乎等于浮动栅极电位。

公开(公告)号：US5661421A

公开(公告)日：1997-08-26

申请号：US507473

申请日：1995-09-29

申请人： Tadahiro Ohmi ,  Tadashi Shibata ,  Koji Kotani

发明人： Tadahiro Ohmi ,  Tadashi Shibata ,  Koji Kotani

IPC分类号： G06F7/04 ,  G06G7/60 ,  G06N3/063 ,  H03K19/21 ,  A03K5/22

CPC分类号： G06N3/0635

摘要： A semiconductor integrated circuit for effecting data matching at high speed is provided in a simple circuit. The semiconductor integrated circuit includes a first input terminal and a second input terminal to which first and second voltage signals representing first and second values are inputted, respectively, and an output terminal. A predetermined output signal is produced at the output terminal when the difference between the first and second values is smaller than a predetermined difference value. The semiconductor integrated circuit of this invention comprises first and second inverters, each inverter comprising neuron MOS transistors having a plurality of input gates. The first and second signals or, first and second processed signals obtained by applying predetermined processing to the first and second signals, are inputted to at least one of the input gates of the inverters.

摘要翻译： PCT No.PCT / JP94 / 00263 Sec。 371 1995年9月29日第 102（e）1995年9月29日PCT PCT 1994年2月22日PCT公布。 WO94 / 19761 PCT出版物 日期1994年9月1日在简单的电路中提供用于高速实现数据匹配的半导体集成电路。 半导体集成电路包括分别输入表示第一和第二值的第一和第二电压信号的第一输入端和第二输入端和输出端。 当第一和第二值之间的差小于预定的差值时，在输出端产生预定的输出信号。 本发明的半导体集成电路包括第一和第二反相器，每个反相器包括具有多个输入门的神经元MOS晶体管。 通过对第一和第二信号应用预定处理而获得的第一和第二信号或第一和第二处理信号被输入至反相器的至少一个输入门。