公开(公告)号：US11362267B2

公开(公告)日：2022-06-14

申请号：US16721789

申请日：2019-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Hsiang Tseng ,  Chih-Lin Wang ,  Yi-Huang Wu

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.

公开(公告)号：US11251088B2

公开(公告)日：2022-02-15

申请号：US16901815

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49

Abstract: A semiconductor device includes an active area having source and drain regions and a channel region between the source and drain regions, an isolation structure surrounding the active area, and a gate structure over the channel region of the active area and over the isolation structure, wherein the isolation structure has a first portion under the gate structure and a second portion free from coverage by the gate structure, and a top of the first portion of the isolation structure is lower than a top of the second portion of the isolation structure.

公开(公告)号：US11177430B2

公开(公告)日：2021-11-16

申请号：US16443772

申请日：2019-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Ya-Jui Tsou ,  Zong-You Luo ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.

公开(公告)号：US10439022B2

公开(公告)日：2019-10-08

申请号：US15830979

申请日：2017-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US10096596B2

公开(公告)日：2018-10-09

申请号：US14970036

申请日：2015-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cong-Min Fang ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.

公开(公告)号：US20180226297A1

公开(公告)日：2018-08-09

申请号：US15943671

申请日：2018-04-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0607 ,  H01L29/49 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621

Abstract: A semiconductor device includes a substrate, an isolation structure, and a gate structure. The substrate has an active area. The isolation structure surrounds the active area of the substrate. The gate structure is across the active area of the substrate. The isolation structure has a first portion under the gate structure and a second portion adjacent to the gate structure. A top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.

公开(公告)号：US09911821B2

公开(公告)日：2018-03-06

申请号：US14940832

申请日：2015-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ruei Yeh ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/518 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a metal gate electrode structure over the semiconductor substrate. The semiconductor device structure includes an insulating layer over the semiconductor substrate and surrounding the metal gate electrode structure. The semiconductor device structure includes a first metal nitride layer over a first top surface of the metal gate electrode structure and in direct contact with the metal gate electrode structure. The first metal nitride layer includes a nitride material of the metal gate electrode structure.

公开(公告)号：US09911691B2

公开(公告)日：2018-03-06

申请号：US15379461

申请日：2016-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Sheng Zheng ,  Chih-Lin Wang

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection structure includes a first dielectric layer, at least one first conductor, and an etch stop layer. The first conductor is disposed partially in the first dielectric layer and has a portion protruding from the first dielectric layer. The etch stop layer is disposed on the first dielectric layer and covers the protruding portion of the first conductor. The etch stop layer has a cap portion on a top surface of the protruding portion of the first conductor and a spacer portion on at least one sidewall of the protruding portion of the first conductor, and the spacer portion is thicker than the cap portion.

公开(公告)号：US20150294914A1

公开(公告)日：2015-10-15

申请号：US14248755

申请日：2014-04-09

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L27/088 ,  H01L21/321 ,  H01L21/311 ,  H01L21/02 ,  H01L21/285 ,  H01L21/28 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0607 ,  H01L29/49 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621

Abstract: A semiconductor device with an increased effective gate length or an increased effective channel width, and a method of forming the same are provided. The effective gate length or the effective channel width of the device is increased by lowering a top surface of an oxide isolation structure below the gate of the semiconductor device.

Abstract translation: 提供了具有增加的有效栅极长度或增加的有效沟道宽度的半导体器件及其形成方法。 通过将半导体器件的栅极下方的氧化物隔离结构的顶表面降低来增加器件的有效栅极长度或有效沟道宽度。

公开(公告)号：US11410714B2

公开(公告)日：2022-08-09

申请号：US16572329

申请日：2019-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Zong-You Luo ,  Ya-Jui Tsou ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: G11C11/16 ,  H01L27/02 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.