公开(公告)号：US20180138056A1

公开(公告)日：2018-05-17

申请号：US15855305

申请日：2017-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L21/50 ,  H01L31/09 ,  H01L31/0232 ,  H01L27/146 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H01L21/311 ,  H01L23/48 ,  H01L23/31 ,  H01L23/29 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L21/563 ,  H01L21/31111 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/82 ,  H01L25/167 ,  H01L25/50 ,  H01L27/14618 ,  H01L31/0232 ,  H01L31/09 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad over a first chip and a second conductive pad over a second chip. A molding structure surrounds the first chip and the second chip. A first passivation layer is over the first chip and the second chip, and a conductive structure is over the first passivation layer. The conductive structure is coupled to the first conductive pad. A second passivation layer is over the conductive structure. The first passivation layer and the second passivation layer have sidewalls defining an aperture that is directly over an optical element within the second chip and that extends through the first passivation layer and the second passivation layer.

公开(公告)号：US20160343697A1

公开(公告)日：2016-11-24

申请号：US15223609

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L21/768 ,  H01L21/311 ,  H01L23/29 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/31111 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/82 ,  H01L25/167 ,  H01L25/50 ,  H01L27/14618 ,  H01L31/0232 ,  H01L31/09 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.

公开(公告)号：US20210104485A1

公开(公告)日：2021-04-08

申请号：US17104588

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/42 ,  H01L23/373 ,  H01L21/56

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip and a second chip attached to a substrate. A thermal conductivity layer is attached to the first chip. A molding compound laterally surrounds the first chip, the second chip, and the thermal conductivity layer. The second chip extends from the substrate to an imaginary horizontally extending line that extends along a horizontally extending surface of the thermal conductivity layer facing away from the substrate. The imaginary horizontally extending line is parallel to the horizontally extending surface.

公开(公告)号：US10957559B2

公开(公告)日：2021-03-23

申请号：US16575698

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.

公开(公告)号：US10748825B2

公开(公告)日：2020-08-18

申请号：US16382542

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/31 ,  H01L23/48 ,  H01L21/50 ,  H01L31/0232 ,  H01L31/09 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L31/0203 ,  H01L33/52 ,  H01L33/48 ,  H01L23/28 ,  H01L23/485 ,  H01L23/00 ,  H01L27/146 ,  H01L33/54 ,  H01L21/311 ,  H01L21/683 ,  H01L21/768 ,  H01L23/29 ,  H01L25/16 ,  H01L25/00

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad disposed over a first substrate and a second conductive pad disposed over a second substrate. The second conductive pad is a multi-layer structure having an uppermost metal layer including titanium or nickel. A molding structure surrounds the first substrate and the second substrate. A conductive structure is over the first substrate and the second substrate. The conductive structure is conductively coupled to the second conductive pad.

公开(公告)号：US20200043838A1

公开(公告)日：2020-02-06

申请号：US16600752

申请日：2019-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/498 ,  H01L23/373 ,  H01L23/433 ,  H01L21/48

Abstract: Some embodiments relate to a semiconductor package. The package includes a substrate having an upper surface and a lower surface. A first chip is disposed over a first portion of the upper surface of the substrate. A second chip is disposed over a second portion of the upper surface of the substrate. A first plurality of carbon nano material pillars are disposed over an uppermost surface of the first chip, and a second plurality of carbon nano material pillars are disposed over an uppermost surface of the second chip. A molding compound is disposed above the substrate, and encapsulates the first chip, the first plurality of carbon nano material pillars, the second chip, and the second plurality of carbon nano material pillars.

公开(公告)号：US20180247912A1

公开(公告)日：2018-08-30

申请号：US15966426

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/42 ,  H01L23/373

CPC classification number: H01L24/29 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/4334 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A method of forming a semiconductor package includes attaching a thermal conductivity layer to a chip. The chip has a first surface and a second surface. The thermal conductivity layer is attached to the first surface of the chip. The thermal conductivity layer provides a path through which heat generated from the chip is dissipated to the ambient. A substrate is attached to the second surface of the chip after attaching the thermal conductivity layer to the chip. A molding compound is formed to encapsulate the chip and the thermal conductivity layer.

公开(公告)号：US09865481B2

公开(公告)日：2018-01-09

申请号：US15223609

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/56 ,  H01L23/48 ,  H01L21/50 ,  H01L23/31 ,  H01L31/0232 ,  H01L31/09 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L27/146 ,  H01L21/311 ,  H01L21/683 ,  H01L21/768 ,  H01L23/29 ,  H01L25/16 ,  H01L25/00

CPC classification number: H01L21/563 ,  H01L21/31111 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/82 ,  H01L25/167 ,  H01L25/50 ,  H01L27/14618 ,  H01L31/0232 ,  H01L31/09 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.