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    Reducing Parasitic Capacitance in Semiconductor Devices
    22.
    发明申请
    Reducing Parasitic Capacitance in Semiconductor Devices 有权

    公开(公告)号：US20220376044A1

    公开(公告)日：2022-11-24

    申请号：US17868678

    申请日：2022-07-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Ta Yu ,  Hsiao-Chiu Hsu ,  Feng-Cheng Yang

    IPC: H01L29/06 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78

    Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

    Memory Array Staircase Structure
    24.
    发明申请
    Memory Array Staircase Structure 有权

    公开(公告)号：US20220366952A1

    公开(公告)日：2022-11-17

    申请号：US17814341

    申请日：2022-07-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

    IPC: G11C8/14 ,  H01L21/822 ,  H01L21/8239 ,  H01L27/105 ,  H01L27/11597

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

    SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURE
    26.
    发明申请
    SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURE 有权

    公开(公告)号：US20220352038A1

    公开(公告)日：2022-11-03

    申请号：US17813086

    申请日：2022-07-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

    IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/311 ,  H01L29/08 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092

    Abstract: A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.

    Conformal transfer doping method for fin-like field effect transistor
    27.
    发明授权
    Conformal transfer doping method for fin-like field effect transistor 有权

    公开(公告)号：US11476352B2

    公开(公告)日：2022-10-18

    申请号：US17121007

    申请日：2020-12-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

    IPC: H01L21/265 ,  H01L21/225 ,  H01L29/66 ,  H01L29/165

    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

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