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    Exposure method and exposure apparatus
    21.
    发明授权
    Exposure method and exposure apparatus 有权

    公开(公告)号：US10747128B2

    公开(公告)日：2020-08-18

    申请号：US15906580

    申请日：2018-02-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yung-Yao Lee ,  Heng-Hsin Liu ,  Hung-Ming Kuo ,  Jui-Chun Peng

    IPC: G03F9/00 ,  G03F7/20 ,  H01L21/67 ,  H01L21/027 ,  H01L21/66

    Abstract: In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.

    LITHO CLUSTER AND MODULIZATION TO ENHANCE PRODUCTIVITY
    23.
    发明申请
    LITHO CLUSTER AND MODULIZATION TO ENHANCE PRODUCTIVITY 有权
    LITHO集群和模块化以提高生产力

    公开(公告)号：US20150076371A1

    公开(公告)日：2015-03-19

    申请号：US14551302

    申请日：2014-11-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

    IPC: H01L21/67 ,  H01J37/20 ,  H01J37/16 ,  H01J37/32 ,  H01J37/317

    CPC classification number: H01L21/67225 ,  G03F7/16 ,  G03F7/30 ,  G03F7/70991 ,  H01J37/16 ,  H01J37/20 ,  H01J37/3174 ,  H01J37/32899 ,  H01L21/67276 ,  H01L21/67745

    Abstract: The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

    Abstract translation: 本公开涉及一种用于半导体工件加工的平版印刷工具装置。 光刻工具装置将光刻工具组合成簇，并且将半导体工件在第一簇中的第一类型的多个光刻工具之间选择性地传输到第二簇中的第二类型的光刻工具。 通过转移组件实现选择性转移，转移组件耦合到识别第一类型的光刻工具中产生的缺陷的缺陷扫描工具。 所公开的平版印刷工具装置还利用共同的结构元件，例如壳体组件和诸如气体和化学品的共享功能元件。 光刻工具装置可以包括被配置成提供这些各种部件的模块化的烘烤，涂覆，曝光和显影单元，以便为给定的光刻制造工艺优化产量和效率。

    Synchronized integrated metrology for overlay-shift reduction
    29.
    发明授权
    Synchronized integrated metrology for overlay-shift reduction 有权

    公开(公告)号：US09841687B2

    公开(公告)日：2017-12-12

    申请号：US14798563

    申请日：2015-07-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yung-Yao Lee ,  Heng-Hsin Liu ,  Jui-Chun Peng ,  Yung-Cheng Chen

    IPC: G03F7/20 ,  G03F9/00

    CPC classification number: G03F7/70633

    Abstract: The present disclosure relates to a method of semiconductor processing. The method includes, receiving a first wafer having a photoresist coating on a face of the first wafer. An exposure unit is used to perform a first number of radiation exposures on the photoresist coating, thereby forming an exposed photoresist coating. The exposed photoresist coating is developed, thereby forming a developed photoresist coating. An OVL measurement zone pattern is selected from a number of different, pre-determined OVL measurement zone patterns based on at least one of: the first number of radiation exposures performed on the first wafer or a previous number of radiation exposures performed on a previously processed wafer, which was processed before the first wafer. A number of OVL measurements are performed on the developed photoresist coating within the selected OVL measurement zone pattern.

    Overlay metrology method
    30.
    发明授权
    Overlay metrology method 有权
    覆盖度量方法

    公开(公告)号：US09164398B2

    公开(公告)日：2015-10-20

    申请号：US14252612

    申请日：2014-04-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yung-Yao Lee ,  Ying-Ying Wang ,  Yi-Ping Hsieh ,  Heng-Hsin Liu

    IPC: G03F7/20 ,  G01B11/14

    CPC classification number: G03F7/70633 ,  G01B11/14 ,  G01B2210/56

    Abstract: A process of measuring overlay metrologies of wafers, the wafer having a plurality of patterned layers. The process begins with retrieving historical overlay metrologies from a database, and real overlay metrologies of a first group of the wafers are measured. On the other hand, virtual overlay metrologies of a second group of the wafers are calculated with the retrieved historical overly metrologies. The real overlay metrologies of the first group of the wafers and the virtual overlay metrologies of the second group of the wafers are stored to the database as the historical overlay metrologies.

    Abstract translation: 测量晶片叠加计量的过程，晶片具有多个图案化层。 该过程开始于从数据库中检索历史叠加计量，并且测量第一组晶片的实际重叠计量。 另一方面，第二组晶片的虚拟覆盖计量学用所检索的历史过度计量来计算。 第一组晶圆的真实覆盖计量学和第二组晶圆的虚拟覆盖计量学作为历史重叠计量存储到数据库。

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