公开(公告)号：US20210225751A1

公开(公告)日：2021-07-22

申请号：US17222118

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yun Chen Hsieh ,  Hui-Jung Tsai ,  Hung-Jui Kuo

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L21/66 ,  H01L21/288 ,  H01L21/3213 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48

Abstract: Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

公开(公告)号：US20210217709A1

公开(公告)日：2021-07-15

申请号：US17215297

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L23/58 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/485 ,  H01L23/00 ,  H01L21/683

Abstract: A method includes encapsulating a package component in an encapsulating material, with the encapsulating material including a portion directly over the package component. The portion of the encapsulating material is patterned to form an opening revealing a conductive feature in the package component. A redistribution line extends into the opening to contact the conductive feature. An electrical connector is formed over and electrically coupling to the conductive feature.

公开(公告)号：US11004812B2

公开(公告)日：2021-05-11

申请号：US16133705

申请日：2018-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Hung-Jui Kuo ,  Hsin-Yu Pan ,  Ming-che Ho ,  Tzu Yun Huang ,  Yen-Fu Su

IPC: H01L23/00

Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.

公开(公告)号：US10998202B2

公开(公告)日：2021-05-04

申请号：US16527015

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L21/56 ,  H01L23/367 ,  H01L23/538 ,  H01L23/544 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31

Abstract: A semiconductor package includes a die and an encapsulant. The die has an active surface and an opposite backside surface. The encapsulant wraps around the die and has a recess reaching the backside surface. A span of the recess differs from a span of the backside surface and a span of the encapsulant. A manufacturing method includes at least the following steps. A blanket die attach film is spin-coated. A light exposure process is performed to the blanket die attach film. Blanket die attach film is developed to form a patterned die adhesive. A die is disposed over the patterned die adhesive with a backside surface closer to the patterned die adhesive. The patterned die adhesive is cured to affix the die. The die and the cured die adhesive are encapsulated in an encapsulant. The cured die adhesive is removed.

公开(公告)号：US10937688B2

公开(公告)日：2021-03-02

申请号：US16396793

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Chen-Cheng Kuo ,  Hung-Jui Kuo

IPC: H01L23/053 ,  H01L21/768 ,  H01L21/56 ,  H01L21/02 ,  H01L23/538 ,  H01L21/78 ,  H01L23/532 ,  H01L23/31 ,  H01L23/00

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

公开(公告)号：US20210020559A1

公开(公告)日：2021-01-21

申请号：US16513727

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tuan-Yu Hung ,  Ching-Feng Yang ,  Hung-Jui Kuo ,  Kai-Chiang Wu ,  Ming-Che Ho

IPC: H01L23/498 ,  H01L23/00 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/28 ,  H01L21/768 ,  H01L21/56 ,  H01L23/66 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.

公开(公告)号：US10790212B2

公开(公告)日：2020-09-29

申请号：US16675227

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3105

Abstract: A method of manufacturing a package structure includes the following processes. An adhesive layer is formed on a carrier. A die is attached to the carrier through the adhesive layer. A protection layer is formed to at least cover a sidewall and a portion of a top surface of the adhesive layer on an edge of the carrier. An encapsulant is formed over the carrier to laterally encapsulate the die. A redistribution layer (RDL) structure is formed on the die and the encapsulant. A connector is formed to electrically connect to the die through the RDL structure. The carrier is released.

公开(公告)号：US20200303211A1

公开(公告)日：2020-09-24

申请号：US16892320

申请日：2020-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Feng Chen ,  Chih-Hua Chen ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hung-Jui Kuo ,  Hui-Jung Tsai ,  Hao-Yi Tsai

IPC: H01L21/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538

Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.

公开(公告)号：US10763206B2

公开(公告)日：2020-09-01

申请号：US15879457

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L21/768 ,  H01L23/00 ,  H01L21/66 ,  H01L23/538 ,  H01L21/683 ,  H01L23/498

Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

公开(公告)号：US20200273805A1

公开(公告)日：2020-08-27

申请号：US16283836

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/532 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768

Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first dielectric layer, a first conductive pattern and a barrier layer. The first conductive pattern is disposed in a second dielectric layer over the first dielectric layer. The barrier layer is disposed at an interface between the first conductive pattern and the second dielectric layer and an interface between the first dielectric layer and the second dielectric layer.