公开(公告)号：US10163651B1

公开(公告)日：2018-12-25

申请号：US15883748

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Tai Hsiao ,  Cheng-Yuan Tsai ,  Hsun-Chung Kuang ,  Yao-Wen Chang

IPC: H01L45/00 ,  H01L21/311 ,  H01L21/3105 ,  H01L43/02 ,  H01L23/528 ,  H01L43/08

Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes. A method for manufacturing the memory cell is also provided.

公开(公告)号：US20170287878A1

公开(公告)日：2017-10-05

申请号：US15626834

申请日：2017-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

IPC: H01L25/065 ,  H01L25/00 ,  H01L27/146 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49838 ,  H01L23/52 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad.

公开(公告)号：US20160379960A1

公开(公告)日：2016-12-29

申请号：US14750003

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49838 ,  H01L23/52 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.

Abstract translation: 本发明涉及一种多维集成芯片，其具有在从背面接合焊盘侧向偏移的集成芯片裸片之间垂直延伸的再分配层。 多维集成芯片具有第一集成芯片裸片，其具有布置在第一半导体衬底的前侧上的第一级间介电层内的第一多个金属互连层。 所述多维集成芯片还具有第二集成芯片裸片，其具有设置在邻接所述第一ILD层的第二层间电介质层内的第二多个金属互连层。 接合焊盘设置在延伸穿过第二半导体衬底的凹部内。 重新分配层在从接合焊盘横向偏移的位置处在第一多个金属互连层和第二多个金属互连层之间垂直地延伸。

公开(公告)号：US12272715B2

公开(公告)日：2025-04-08

申请号：US17353003

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Hau-Yi Hsiao ,  Che Wei Yang ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai

IPC: H01L27/146 ,  H01L21/768

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.

公开(公告)号：US12176370B2

公开(公告)日：2024-12-24

申请号：US17336852

申请日：2021-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Sheng-Chau Chen ,  Feng-Chi Hung ,  Sheng-Chan Li

IPC: H01L27/146

Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.

公开(公告)号：US11735624B2

公开(公告)日：2023-08-22

申请号：US17361723

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Ru-Liang Lee ,  Ming Chyi Liu ,  Sheng-Chan Li ,  Sheng-Chau Chen

IPC: H01L27/146 ,  H01L49/02 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L28/87 ,  H01L21/768 ,  H01L23/5223 ,  H01L28/90 ,  H01L27/14603

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.

公开(公告)号：US20220310678A1

公开(公告)日：2022-09-29

申请号：US17353003

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Hau-Yi Hsiao ,  Che Wei Yang ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai

IPC: H01L27/146 ,  H01L21/768

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.

公开(公告)号：US20220293647A1

公开(公告)日：2022-09-15

申请号：US17197291

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Ming-Che Lee

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards a pixel sensor. The pixel sensor includes a substrate having a front-side opposite a back-side. An image sensor element comprises an active layer disposed within the substrate, where the active layer comprises germanium. An anti-reflective coating (ARC) structure overlies the back-side of the substrate. The ARC structure includes a first dielectric layer overlying the back-side of the substrate, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer. A first index of refraction of the first dielectric layer is less than a second index of refraction of the second dielectric layer, and a third index of refraction of the third dielectric layer is less than the first index of refraction.

公开(公告)号：US20220293457A1

公开(公告)日：2022-09-15

申请号：US17197330

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Tzu-Jui Wang ,  Sheng-Chan Li

IPC: H01L21/762 ,  H01L27/146

Abstract: In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.

公开(公告)号：US11152276B2

公开(公告)日：2021-10-19

申请号：US16785866

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu

IPC: H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L21/56 ,  H01L25/065

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.