公开(公告)号：US12300698B2

公开(公告)日：2025-05-13

申请号：US18355143

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

公开(公告)号：US20240363397A1

公开(公告)日：2024-10-31

申请号：US18767134

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L21/762 ,  G06F30/392 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L21/76283 ,  H01L21/845 ,  H01L29/0649 ,  G06F30/392

Abstract: A semiconductor structure includes a first well doped with a first dopant and a second well doped with a second dopant different from the first dopant. From a top view, the first well includes a first base extending lengthwise along a direction, and a first letter-shaped portion and a second letter-shaped portion connected to the first base. From the top view, the second well includes a second base extending lengthwise along the direction and a third letter-shaped portion connected to the second base. The third letter-shaped portion extends into the first well and is keyed to the first letter-shaped portion and the second letter-shaped portion.

公开(公告)号：US11990525B2

公开(公告)日：2024-05-21

申请号：US17826816

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang ,  Jhon Jhy Liaw

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/785 ,  H01L2029/7858

Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US11749683B2

公开(公告)日：2023-09-05

申请号：US17728243

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang

IPC: H10B10/00 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L27/0924 ,  H01L21/762 ,  H01L21/76831 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851 ,  H10B10/12

Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

公开(公告)号：US20220293752A1

公开(公告)日：2022-09-15

申请号：US17826816

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuan-Lin Yeh ,  Chun-Jun Lin ,  Kuo-Hua Pan ,  Mu-Chi Chiang ,  Jhon Jhy Liaw

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US20220238519A1

公开(公告)日：2022-07-28

申请号：US17717296

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.

公开(公告)号：US11239339B2

公开(公告)日：2022-02-01

申请号：US16397248

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Jhon Jhy Liaw ,  Kuo-Hua Pan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L21/308 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786

Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.

公开(公告)号：US20210384311A1

公开(公告)日：2021-12-09

申请号：US17409086

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shien-Yang Wu ,  Ta-Chun Lin ,  Kuo-Hua Pan

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3065 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L21/306 ,  H01L29/40 ,  H01L29/165

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

公开(公告)号：US20210305084A1

公开(公告)日：2021-09-30

申请号：US17150725

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC: H01L21/764 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

公开(公告)号：US09559134B2

公开(公告)日：2017-01-31

申请号：US14564196

申请日：2014-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Jung-I Lin ,  Ta-Chun Lin ,  Tien-Lu Lin ,  Chen-Jong Wang

IPC: H01L27/148 ,  H01L29/768 ,  H01L29/00 ,  H01L27/146 ,  H01L27/092 ,  H01L29/94 ,  H01L27/12

CPC classification number: H01L21/764 ,  H01L21/76224 ,  H01L21/76227 ,  H01L21/76289 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/0921 ,  H01L27/1203 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L29/945

Abstract: An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided.

Abstract translation: 提供了采用深沟槽间隔隔离的图像传感器。 多个像素传感器布置在半导体衬底之上或之内。 沟槽在多个像素传感器周围和相邻的像素传感器之间并且在半导体衬底中布置，并且沟槽在沟槽的侧壁之间具有间隙。 在覆盖间隙的位置处，在沟槽之上或之内布置盖。 盖子密封沟槽内的间隙。 还提供了一种制造图像传感器的方法。