公开(公告)号：US20200343176A1

公开(公告)日：2020-10-29

申请号：US16927249

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Hsin-Yu Chen ,  Lin-Chih Huang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/528 ,  H01L27/088 ,  H01L23/31 ,  H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768

Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.

公开(公告)号：US10396014B2

公开(公告)日：2019-08-27

申请号：US15859872

申请日：2018-01-02

Applicant: Taiwan Semiconductor Manufacturing Co Ltd

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L21/768

Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.

公开(公告)号：US20180145012A1

公开(公告)日：2018-05-24

申请号：US15859872

申请日：2018-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.

公开(公告)号：US20250062247A1

公开(公告)日：2025-02-20

申请号：US18503853

申请日：2023-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yang-Chih Hsueh ,  Yan-Zuo Tsai ,  Ming-Tsu Chung ,  Yung-Chi Lin

IPC: H01L23/00 ,  H01L21/3115 ,  H01L21/66 ,  H01L23/528

Abstract: A method includes depositing a dielectric layer on a package component having a first warpage, and performing an implantation process to implant the dielectric layer with a stress modulation dopant. After the implantation process, the package component has a second warpage smaller than the first warpage.

公开(公告)号：US12087732B2

公开(公告)日：2024-09-10

申请号：US18338013

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Ku-Feng Yang ,  Yung-Chi Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/683 ,  H01L21/82 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/6836 ,  H01L21/82 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582

Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.

公开(公告)号：US12015008B2

公开(公告)日：2024-06-18

申请号：US17869977

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  B23K26/362 ,  H01L21/3213 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/80 ,  B23K26/362 ,  H01L21/32136 ,  H01L24/03 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/37001

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

公开(公告)号：US11973055B2

公开(公告)日：2024-04-30

申请号：US17869977

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  B23K26/362 ,  H01L21/3213 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/80 ,  B23K26/362 ,  H01L21/32136 ,  H01L24/03 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/37001

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

公开(公告)号：US20240105632A1

公开(公告)日：2024-03-28

申请号：US18525966

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/97 ,  H01L24/16 ,  H01L25/0652

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US20240088123A1

公开(公告)日：2024-03-14

申请号：US18518187

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yung-Chi Lin ,  Wen-Chih Chiou

IPC: H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08146 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/33519 ,  H01L2224/80006 ,  H01L2224/8083 ,  H01L2224/83005 ,  H01L2224/8383 ,  H01L2224/83896 ,  H01L2224/92142 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

公开(公告)号：US20250158005A1

公开(公告)日：2025-05-15

申请号：US18388326

申请日：2023-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ming Chen ,  Yung-Chi Lin

IPC: H01L25/00 ,  H01L23/00 ,  H01L25/065

Abstract: A wafer on wafer on wafer and a chip on wafer on wafer structure and methods of forming the same are provided. In accordance with some embodiments, a first device wafer is bonded to a first carrier through wafer-on-wafer bonding and additional device wafers may subsequently be bonded to the first device wafer. A support wafer is then bonded to the top most device wafer and the first wafer may then be removed. The bonded wafer structure may then be singulated into individual semiconductor device packages. Through the wafer-on-wafer bonding process, the manufacturing cost and cycle time may be reduced.