公开(公告)号：US20230268224A1

公开(公告)日：2023-08-24

申请号：US18309131

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Po-Cheng Shih ,  Syun-Ming Jang ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/027 ,  G03F7/20 ,  G03F7/038 ,  G03F7/039

CPC classification number: H01L21/76823 ,  H01L21/76802 ,  H01L21/0274 ,  G03F7/2022 ,  G03F7/038 ,  G03F7/039 ,  G03F7/2004 ,  H01L21/76877

Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

公开(公告)号：US20230163163A1

公开(公告)日：2023-05-25

申请号：US17717731

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Zhong Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L49/02

CPC classification number: H01L28/87

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming an etch stop layer over the interconnect structure; and forming a first multi-layered structure over the etch stop layer, which includes: forming a first conductive layer over the etch stop layer; treating an upper layer of the first conductive layer with a plasma process; and forming a second conductive layer over the treated first conductive layer. The method further includes: patterning the first multi-layered structure to form a first electrode; forming a first dielectric layer over the first electrode; forming a second multi-layered structure over the first dielectric layer, the second multi-layered structure having the same layered structure as the first multi-layered structure; and patterning the second multi-layered structure to form a second electrode.

公开(公告)号：US11441221B2

公开(公告)日：2022-09-13

申请号：US17018797

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsien Cheng ,  Chung-Ting Ko ,  Tsung-Hsun Yu ,  Tze-Liang Lee ,  Chi On Chui

IPC: H01L21/02 ,  H01L21/033 ,  C23C16/455 ,  C23C16/40 ,  H01L21/8238

Abstract: In an embodiment, a method of manufacturing a semiconductor device includes preparing a deposition processing chamber by flowing first precursors to form a dielectric coat along an inner sidewall of the deposition processing chamber and flowing a second precursor to form a hydrophobic layer over the dielectric coat. In addition one or more deposition cycles are performed. Next, the second precursor is flowed again to repair the hydrophobic layer.

公开(公告)号：US11282712B2

公开(公告)日：2022-03-22

申请号：US16725564

申请日：2019-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Hau Shiu ,  Chung-Chi Ko ,  Tze-Liang Lee ,  Yu-Yun Peng

IPC: H01L21/311 ,  H01L21/02 ,  G03F7/09 ,  H01L21/768

Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film.

公开(公告)号：US11271083B2

公开(公告)日：2022-03-08

申请号：US16805862

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsien Cheng ,  Jr-Hung Li ,  Tai-Chun Huang ,  Tze-Liang Lee ,  Chung-Ting Ko ,  Jr-Yu Chen ,  Wan-Chen Hsieh

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

公开(公告)号：US20210343529A1

公开(公告)日：2021-11-04

申请号：US17377813

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Chang ,  Jung-Hau Shiu ,  Jen Hung Wang ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.

公开(公告)号：US11164789B1

公开(公告)日：2021-11-02

申请号：US16852191

申请日：2020-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsai-Jung Ho ,  Yu-Shih Wang ,  Tze-Liang Lee

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/467 ,  H01L21/321 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

Abstract: A method includes forming a dummy gate structure over a substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; forming an interlayer dielectric (ILD) layer surrounding the gate spacers; replacing the dummy gate structure with a metal gate structure; etching back the metal gate structure to form a gate trench between the gate spacers; depositing a first dielectric layer in the gate trench, in which the first dielectric layer has horizontal portions over the metal gate structure and the ILD layer, and vertical portions on sidewalls of the gate spacers; etching the vertical portions of the first dielectric layer until the sidewalls of the gate spacers exposed; and performing depositing the first dielectric layer and etching the vertical portions of the first dielectric layer in an alternate manner.

公开(公告)号：US20210262090A1

公开(公告)日：2021-08-26

申请号：US17018797

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsien Cheng ,  Chung-Ting Ko ,  Tsung-Hsun Yu ,  Tze-Liang Lee ,  Chi On Chui

IPC: C23C16/455 ,  H01L21/033 ,  H01L21/02 ,  C23C16/40

Abstract: In an embodiment, a method of manufacturing a semiconductor device includes preparing a deposition processing chamber by flowing first precursors to form a dielectric coat along an inner sidewall of the deposition processing chamber and flowing a second precursor to form a hydrophobic layer over the dielectric coat. In addition one or more deposition cycles are performed. Next, the second precursor is flowed again to repair the hydrophobic layer.

公开(公告)号：US20210184037A1

公开(公告)日：2021-06-17

申请号：US17169994

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Chang Sung ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li ,  Tsz-Mei Kwok

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088 ,  H01L21/02 ,  H01L29/165

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

公开(公告)号：US20210119048A1

公开(公告)日：2021-04-22

申请号：US17110592

申请日：2020-12-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/04 ,  H01L29/08 ,  H01L29/165

Abstract: The present disclosure relates to a method of forming a transistor device. The method may be performed by forming a gate structure onto a semiconductor substrate and forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure. One or more strain inducing materials are formed within the source/drain recess. The one or more strain inducing materials include a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the one or more strain inducing materials to a position above the bottommost surface. The bottommost surface contacts the semiconductor substrate.