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公开(公告)号：US11417729B2
公开(公告)日：2022-08-16
申请号：US16837261
申请日：2020-04-01
发明人： Chao-Ching Cheng , Tzu-Ang Chao , Chun-Chieh Lu , Hung-Li Chiang , Tzu-Chiang Chen , Lain-Jong Li
IPC分类号： H01L29/06 , H01L51/05 , H01L51/00 , H01L21/02 , H01L29/786 , H01L29/66 , H01L29/24 , H01L29/423
摘要： A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.
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公开(公告)号：US20220139822A1
公开(公告)日：2022-05-05
申请号：US17575660
申请日：2022-01-14
发明人： Chia-Cheng Ho , Chun-Chieh Lu , Chih-Sheng Chang
IPC分类号： H01L23/522 , H01L21/768 , H01L29/78 , H01L29/66 , H01L49/02
摘要： A semiconductor device includes a semiconductor fin, a gate structure, a capacitor structure, a conductive contact, and a hard mask layer. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer. The conductive contact is disposed on the capacitor structure. The hard mask layer laterally surrounds the conductive contact. The conductive contact protrudes from a top surface of the hard mask layer.
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公开(公告)号：US11302529B2
公开(公告)日：2022-04-12
申请号：US16925267
申请日：2020-07-09
发明人： Chun-Chieh Lu , Sai-Hooi Yeong , Yu-Ming Lin
IPC分类号： H01L21/28 , H01L21/02 , H01L27/1159
摘要： A method includes: providing a bottom layer; depositing a first seed layer over the bottom layer, the first seed layer having at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom layer adjacent to the first seed layer, the dielectric layer including an amorphous crystal phase; depositing an upper layer over the dielectric layer; performing a thermal operation on the dielectric layer; and cooling the dielectric layer, wherein after the cooling the dielectric layer becomes a ferroelectric layer.
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公开(公告)号：US10854708B2
公开(公告)日：2020-12-01
申请号：US16682381
申请日：2019-11-13
发明人： Chewn-Pu Jou , Chih-Hsin Ko , Po-Wen Chiu , Chao-Ching Cheng , Chun-Chieh Lu , Chi-Feng Huang , Huan-Neng Chen , Fu-Lung Hsueh , Clement Hsingjen Wann
IPC分类号： H01L49/02 , H01L23/528 , H01G4/008 , H01G4/005 , H01L23/522 , H01L23/532 , H01L21/768
摘要： A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
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公开(公告)号：US12041776B2
公开(公告)日：2024-07-16
申请号：US18359181
申请日：2023-07-26
发明人： Chun-Chieh Lu , Sai-Hooi Yeong , Yu-Ming Lin
IPC分类号： H10B43/27 , H01L23/522 , H10B41/10 , H10B41/27 , H10B43/10
CPC分类号： H10B43/27 , H01L23/5221 , H10B41/10 , H10B41/27 , H10B43/10
摘要： A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.
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公开(公告)号：US20240055517A1
公开(公告)日：2024-02-15
申请号：US17886472
申请日：2022-08-12
发明人： Kuo-Chang Chiang , Yu-Chuan Shih , Chun-Chieh Lu , Po-Ting Lin , Hai-Ching Chen , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
IPC分类号： H01L29/78 , H01L27/1159 , H01L29/51 , H01L29/66
CPC分类号： H01L29/78391 , H01L27/1159 , H01L29/516 , H01L29/6684
摘要： Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.
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公开(公告)号：US11869766B2
公开(公告)日：2024-01-09
申请号：US17709284
申请日：2022-03-30
发明人： Chun-Chieh Lu , Sai-Hooi Yeong , Yu-Ming Lin
CPC分类号： H01L21/02516 , H01L21/02472 , H10B51/30
摘要： A method includes: providing a bottom layer; forming a first transistor over a substrate; forming a bottom electrode over the transistor; depositing a first seed layer over the bottom electrode; performing a surface treatment on the first seed layer, wherein after the surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom layer adjacent to the first seed layer, the dielectric layer including an amorphous crystal phase; depositing an upper layer over the dielectric layer; performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.
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公开(公告)号：US11757045B2
公开(公告)日：2023-09-12
申请号：US17571561
申请日：2022-01-10
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78675 , H01L29/66757 , H01L29/78684
摘要： A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.
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公开(公告)号：US20220384658A1
公开(公告)日：2022-12-01
申请号：US17883699
申请日：2022-08-09
IPC分类号： H01L29/78 , H01L29/66 , H01L29/786 , H01L21/447 , H01L21/383 , H01L29/49
摘要： In some embodiments of the present disclosure, a method for forming a semiconductor device is described. A semiconductor layer is formed and a dielectric layer is formed. A pressurized treatment is performed to transform the semiconductor layer into a low-doping semiconductor layer and transform the dielectric layer into a crystalline ferroelectric layer. A gate layer is formed. An insulating layer is formed over the gate layer, the crystalline ferroelectric layer and the low-doping semiconductor layer. Contact openings are formed in the insulating layer exposing portions of the low-doping semiconductor layer. Source and drain terminals are formed on the low-doping semiconductor layer.
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公开(公告)号：US20220384459A1
公开(公告)日：2022-12-01
申请号：US17880803
申请日：2022-08-04
发明人： Chun-Chieh Lu , Han-Jong Chia , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin
IPC分类号： H01L27/1159 , H01L27/11597 , H01L29/66 , H01L29/786
摘要： Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.
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