公开(公告)号：US5222041A

公开(公告)日：1993-06-22

申请号：US735004

申请日：1991-07-25

申请人： Miki Nishimori ,  Hidenori Nomura

发明人： Miki Nishimori ,  Hidenori Nomura

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/409

CPC分类号： G11C7/1069 ,  G11C7/1051

摘要： A data amplifying system in a semiconductor memory includes a current mirror circuit for receiving, via a data bus, an input signal corresponding to data read out from a memory cell via a pair of bit lines and for amplifying the input signal. The current mirror circuit operates on the basis of a power supply voltage. An amplitude limit circuit receives an operation voltage and limits the amplitude of the input signal on the data bus to a predetermined potential range on the basis of the operation voltage. A bit line reset potential generator generates a bit line reset potential and applies the bit line reset potential to the bit lines and the amplitude limit circuit. The bit line reset voltage is lower than the power supply line and serves as the operation voltage applied to the amplitude limit circuit.

公开(公告)号：US06607798B1

公开(公告)日：2003-08-19

申请号：US09530502

申请日：2000-07-20

申请人： Toru Watanabe ,  Shigehiro Matsuno ,  Naoyuki Kondo ,  Takayuki Hoshino ,  Hidenori Nomura

发明人： Toru Watanabe ,  Shigehiro Matsuno ,  Naoyuki Kondo ,  Takayuki Hoshino ,  Hidenori Nomura

IPC分类号： B29D2300

CPC分类号： B32B27/12 ,  B29C70/525 ,  B29L2023/00 ,  B32B1/00 ,  B32B3/20 ,  B32B5/28 ,  B32B27/302 ,  B32B27/36 ,  B32B2325/00 ,  B32B2355/02 ,  B32B2367/00 ,  E04G1/153 ,  Y10T428/12479 ,  Y10T428/13 ,  Y10T428/1328 ,  Y10T428/1352 ,  Y10T428/1376 ,  Y10T428/249953

摘要： Center cores are formed by extrusion-molding ABS resin. Seven pieces of the center cores, which are juxtaposed to each other in the horizontal direction, are supplied by a pultruder, and reinforcing long-fibers impregnated with an unsaturated polyester resin are allowed to pass through dispersion guides and squeezing nozzles, to thus squeezing-mold a fiber-reinforced composite hollow structure having FRP made legs. A final squeezing nozzle is disposed in a cross head die through a cooling jacket, and the hollow structure thus molded is allowed to pass therethrough to be covered with the ABS resin in a state in which the outer periphery of the hollow structure is heated. The hollow structure thus covered is subjected to cooled-sizing through a plurality of horizontal and vertical pairs of rollers, and then cured in a hot curing tank. The surface covered with the ABS resin is subjected to a surface-treatment of imparting irregularities for giving an antislipping function to the surface. A thermoplastic resin-made protective cap is fitted to an end of the center core. The apparatus for manufacturing a composite hollow structure has a plurality of pairs of rotatable and heat-resisting sizing rollers. The plurality of pairs of the sizing rollers are disposed in the pultruding direction while being gradually cooled in the order from those positioned on the upstream side to those positioned on the downstream side for sizing the softened outer layer covering the outer periphery of the intermediate layer.

摘要翻译： 中心芯通过挤出成型ABS树脂形成。 七个在水平方向上相互并列的中心芯由拉拔机提供，并且使浸渍有不饱和聚酯树脂的增强长纤维通过分散导向器和挤压喷嘴，从而挤压 - 模制具有FRP制成的腿的纤维增强复合中空结构。 最后挤压喷嘴通过冷却套管设置在十字头模具中，并且在加热中空结构的外周的状态下，使由此模制的中空结构被允许穿过其被ABS树脂覆盖。 如此覆盖的中空结构通过多个水平和垂直的辊对进行冷却定型，然后在热固化罐中固化。 用ABS树脂覆盖的表面进行表面处理，赋予表面防滑功能。 热塑性树脂制保护帽安装在中心芯的一端。 用于制造复合中空结构的装置具有多对可旋转和耐热的上浆辊。 多个定型辊成对设置在拉拔方向上，同时从位于上游侧的位置到位于下游侧的位置逐渐冷却，以便对覆盖中间层的外周的软化外层进行定径。

公开(公告)号：US5508965A

公开(公告)日：1996-04-16

申请号：US305722

申请日：1994-09-14

申请人： Hidenori Nomura ,  Kenji Nagai ,  Masami Nakashima ,  Hiroshi Yamamoto ,  Isaya Sobue

发明人： Hidenori Nomura ,  Kenji Nagai ,  Masami Nakashima ,  Hiroshi Yamamoto ,  Isaya Sobue

IPC分类号： G11C7/06 ,  G11C11/406 ,  G11C11/4091 ,  G11C7/02

CPC分类号： G11C11/406 ,  G11C11/4091 ,  G11C7/065

摘要： A semiconductor memory device is disclosed, which is supplied with power from a power supply and which includes memory cells and a sense amplifier connected to the cells via bit lines. The memory device further includes a circuit for enabling the sense amplifier in response to a supplied enable signal, and for allowing the sense amplifier to rewrite cell data, read on the bit lines, into the memory cell again in self-refresh mode. The enabling circuit incorporates a noise suppression circuit which suppresses rapid changes in an operation current flowing between the power supply and the sense amplifier in order to minimize power supply related noise.

摘要翻译： 公开了一种半导体存储器件，其从电源提供电力，并且包括存储器单元和经由位线连接到单元的读出放大器。 存储器件还包括一个电路，用于响应所提供的使能信号使读出放大器能够使能，并且允许读出放大器在自刷新模式下再次将位线上的单元数据重新读入存储器单元。 使能电路包括噪声抑制电路，其抑制在电源和读出放大器之间流动的工作电流的快速变化，以便最小化与电源相关的噪声。

公开(公告)号：US5278788A

公开(公告)日：1994-01-11

申请号：US665865

申请日：1991-03-07

申请人： Hidenori Nomura

发明人： Hidenori Nomura

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C7/1048

摘要： In a semiconductor memory device wherein a difference in potential of two data buses is increased during a write mode and is reduced during a read mode, a write/restoring circuit is provided for carrying out a write operation which increases the difference in potential between the data buses and a restoring operation which reduces the increased difference in potential of the data buses to carry out a read operation after the write operation in accordance with a common write control signal using common output transistors.

摘要翻译： 在写入模式期间两个数据总线的电位差增加并且在读取模式期间减小的半导体存储器件中，提供写入/恢复电路用于执行增加数据之间的电位差的写入操作 总线和恢复操作，其减少数据总线的电位差增加，以便根据使用公共输出晶体管的公共写入控制信号在写入操作之后执行读取操作。

公开(公告)号：US4821232A

公开(公告)日：1989-04-11

申请号：US97556

申请日：1987-09-16

申请人： Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

发明人： Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/20 ,  G11C13/00 ,  G11C11/40

CPC分类号： G11C7/20 ,  G11C7/1048

摘要： A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells arranged in a matrix arrangement, a sense amplifier, operatively connected to the memory cell array, amplifying a signal read out from one of the memory cells and having a pair of output terminals for outputting a complementary signal, a pair of data buses for transferring the complementary signal, a transfer gate for connecting the pair of output terminals to the pair of data buses responsive to a read operation, a data output buffer connected to the pair of data buses for outputting an output signal, and a reset circuit for resetting the pair of data buses to a predetermined voltage before each read operation responsive to a reset clock signal. The reset circuit comprises a first circuit connected to the pair of data buses for connecting the pair of data buses to a common node responsive to the reset clock signal, and a second circuit connected between the common node and a ground voltage for shifting a potential at the common node to a voltage which is the predetermined voltage greater than the ground voltage.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括以矩阵布置的多个存储单元，读出放大器，可操作地连接到存储单元阵列，放大从一个存储单元读出的信号，并具有一对输出 用于输出互补信号的端子，用于传送互补信号的一对数据总线，用于响应于读取操作将一对输出端连接到该对数据总线的传输门，连接到该对数据的数据输出缓冲器 用于输出输出信号的总线;以及复位电路，用于响应于复位时钟信号在每次读取操作之前将该对数据总线复位到预定电压。 复位电路包括连接到该对数据总线的第一电路，用于响应于复位时钟信号将一对数据总线连接到公共节点，以及连接在公共节点和接地电压之间的第二电路， 该公共节点为大于接地电压的预定电压的电压。

公开(公告)号：US5619465A

公开(公告)日：1997-04-08

申请号：US584471

申请日：1996-01-11

申请人： Hidenori Nomura ,  Kenji Nagai ,  Masami Nakashima ,  Hiroshi Yamamoto ,  Isaya Sobue

发明人： Hidenori Nomura ,  Kenji Nagai ,  Masami Nakashima ,  Hiroshi Yamamoto ,  Isaya Sobue

IPC分类号： G11C7/06 ,  G11C11/406 ,  G11C11/4091 ,  G11C7/02

CPC分类号： G11C11/406 ,  G11C11/4091 ,  G11C7/065

摘要： A semiconductor memory device is disclosed, which is supplied with power from a power supply and which includes memory cells and a sense amplifier connected to the cells via bit lines. The memory device further includes a circuit for enabling the sense amplifier in response to a supplied enable signal, and for allowing the sense amplifier to rewrite cell data, read on the bit lines, into the memory cell again in self-refresh mode. The enabling circuit incorporates a noise suppression circuit which suppresses rapid changes in an operation current flowing between the power supply and the sense amplifier in order to minimize power supply related noise.

摘要翻译： 公开了一种半导体存储器件，其从电源提供电力，并且包括存储器单元和经由位线连接到单元的读出放大器。 存储器件还包括一个电路，用于响应所提供的使能信号使读出放大器能够使能，并且允许读出放大器在自刷新模式下再次将位线上的单元数据重新读入存储器单元。 使能电路包括噪声抑制电路，其抑制在电源和读出放大器之间流动的工作电流的快速变化，以便最小化与电源相关的噪声。

公开(公告)号：US5349219A

公开(公告)日：1994-09-20

申请号：US175674

申请日：1993-12-30

申请人： Toshiaki Murao ,  Takeo Kikuchi ,  Toshihiko Iryu ,  Hidenori Nomura ,  Hiroyuki Sugamoto

发明人： Toshiaki Murao ,  Takeo Kikuchi ,  Toshihiko Iryu ,  Hidenori Nomura ,  Hiroyuki Sugamoto

IPC分类号： H01L27/02 ,  H01L27/10 ,  H01L27/15

CPC分类号： H01L27/0207

摘要： A wafer-scale semiconductor integrated circuit device includes a wafer, a plurality of chips formed on the wafer, each of the chips having an internal logic circuit, interconnection lines mutually connecting the chips, and clamping circuits which are coupled to chips from among the chips which are located at a periphery of an arrangement of the chips and which prevent the interconnection lines related to the chips located at the periphery from being in a floating state.

摘要翻译： 晶片级半导体集成电路器件包括晶片，形成在晶片上的多个芯片，每个芯片具有内部逻辑电路，互连芯片的互连线以及与芯片之间的芯片耦合的钳位电路 其位于芯片的布置的周边，并且防止与位于周边的芯片相关的互连线处于浮置状态。

公开(公告)号：US5239508A

公开(公告)日：1993-08-24

申请号：US730723

申请日：1991-07-16

申请人： Hidenori Nomura ,  Yoshiharu Kato ,  Eisaku Itoh

发明人： Hidenori Nomura ,  Yoshiharu Kato ,  Eisaku Itoh

IPC分类号： G11C11/409 ,  G11C7/10 ,  H03F1/30

CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

摘要： A semiconductor memory device comprises a memory cell array including a plurality of memory cells, a plurality of word lines and bit lines connected to the memory cells, a data bus for carrying data to be written in and/or read out from a selected memory cell, an addressing circuit for selecting one of the word lines and bit lines, an input buffer for outputting the electric signal indicative of the data to be written on the data bus, a current-mirror amplifier connected to the data bus for amplifying the electric signals that are read out from the memory cell on the data bus, and a limiter circuit connected to the data bus for limiting a voltage swing of the electric signals on the data bus. The limiter circuit maintains the data bus at a predetermined voltage level and limits the voltage level of the electric signals supplied to the current-mirror amplifier, wherein the limiter circuit changes the predetermined voltage level in response to a voltage level of a supply voltage that powers the current-mirror amplifier.

公开(公告)号：US5032889A

公开(公告)日：1991-07-16

申请号：US585515

申请日：1990-09-20

申请人： Toshiaki Murao ,  Takeo Kikuchi ,  Toshihiko Iryu ,  Hiroyuki Sugamoto ,  Hidenori Nomura

发明人： Toshiaki Murao ,  Takeo Kikuchi ,  Toshihiko Iryu ,  Hiroyuki Sugamoto ,  Hidenori Nomura

IPC分类号： H01L21/3205 ,  H01L23/52 ,  H01L23/528

CPC分类号： H01L23/5286 ,  H01L23/52 ,  H01L24/48 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/85205 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/30107

摘要： A wafer-scale integrated circuit includes a plurality of functional blocks, a plurality of respectively corresponding connection terminals being provided in each of the functional blocks. Respectively corresponding pluralities of layered wirings and bonding wires interconnect predetermined, respective ones of said corresponding connection terminals in parallel for supplying power source and other voltages in common to the plurality of functional blocks. The parallel interconnections by the layered wirings and bonding wires, due to different, respective failure modes, affording increased reliability.

公开(公告)号：US4807192A

公开(公告)日：1989-02-21

申请号：US90988

申请日：1987-08-31

申请人： Masao Nakano ,  Hirohiko Mochizuki ,  Tsuyoshi Ohira ,  Yukinori Kodama ,  Hidenori Nomura

发明人： Masao Nakano ,  Hirohiko Mochizuki ,  Tsuyoshi Ohira ,  Yukinori Kodama ,  Hidenori Nomura

IPC分类号： G11C7/10 ,  G11C8/04 ,  G11C11/40 ,  G11C13/00

CPC分类号： G11C7/1018 ,  G11C8/04

摘要： A memory device employing address multiplexing comprises a counter. An external address is initially set in the counter and a counter address value is incremented responsive to toggle of a column address strobe. The counted address value in the counter is supplied as an address signal directly to a column decoder or indirectly to the column decoder through an address buffer. The memory device may be provided with a switching logic circuit which switches the address bits in the counter depending on switching information so that it is possible to arbitrarily determine which address bits in the counter are to determine a nibble address.