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公开(公告)号：US4821232A
公开(公告)日：1989-04-11
申请号：US97556
申请日：1987-09-16
IPC分类号： G11C11/409 , G11C7/10 , G11C7/20 , G11C13/00 , G11C11/40
CPC分类号： G11C7/20 , G11C7/1048
摘要： A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells arranged in a matrix arrangement, a sense amplifier, operatively connected to the memory cell array, amplifying a signal read out from one of the memory cells and having a pair of output terminals for outputting a complementary signal, a pair of data buses for transferring the complementary signal, a transfer gate for connecting the pair of output terminals to the pair of data buses responsive to a read operation, a data output buffer connected to the pair of data buses for outputting an output signal, and a reset circuit for resetting the pair of data buses to a predetermined voltage before each read operation responsive to a reset clock signal. The reset circuit comprises a first circuit connected to the pair of data buses for connecting the pair of data buses to a common node responsive to the reset clock signal, and a second circuit connected between the common node and a ground voltage for shifting a potential at the common node to a voltage which is the predetermined voltage greater than the ground voltage.
摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括以矩阵布置的多个存储单元，读出放大器，可操作地连接到存储单元阵列，放大从一个存储单元读出的信号，并具有一对输出 用于输出互补信号的端子，用于传送互补信号的一对数据总线，用于响应于读取操作将一对输出端连接到该对数据总线的传输门，连接到该对数据的数据输出缓冲器 用于输出输出信号的总线;以及复位电路，用于响应于复位时钟信号在每次读取操作之前将该对数据总线复位到预定电压。 复位电路包括连接到该对数据总线的第一电路，用于响应于复位时钟信号将一对数据总线连接到公共节点，以及连接在公共节点和接地电压之间的第二电路， 该公共节点为大于接地电压的预定电压的电压。
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公开(公告)号：US4799197A
公开(公告)日：1989-01-17
申请号：US91795
申请日：1987-09-01
IPC分类号： G11C11/401 , G11C7/10 , G11C7/18 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C7/00 , G11C11/24
CPC分类号： G11C11/4097 , G11C11/4091 , G11C7/1006 , G11C7/18
摘要： A semiconductor memory device comprises a memory cell array comprising memory cells; a plurality of pairs of bit lines which are coupled to the memory cells and a data bus, each bit line being divided into at least two pairs of bit line parts; at least one sense amplifier provided between the pairs of bit line parts in each of the pairs of bit lines, for sensing a difference in potential between bit line parts in each pair, the sense amplifier being formed with complementary metal oxide semiconductor transistors; and at least a pair of transfer gates provided between a non-data bus side and a data bus side of the sense amplifier, the pair of transfer gates being held in an off-state when the sense amplifier is activated.
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公开(公告)号：US4870617A
公开(公告)日：1989-09-26
申请号：US97558
申请日：1987-09-16
IPC分类号： G11C11/409 , G11C5/06 , G11C7/10 , G11C11/401
CPC分类号： G11C5/063 , G11C7/1048
摘要： A semiconductor memory device comprises a plurality of reset circuits connected to a data bus pair at different locations. Before each read operation, the reset circuits reset the data bus pair to a predetermined reset voltage. The resetting of the data bus pair is virtually unaffected by the distributed resistances and parasitic capacitances of the data bus pair, since the resetting is carried out at a plurality of locations on the data bus pair.
摘要翻译： 半导体存储器件包括在不同位置连接到数据总线对的多个复位电路。 在每次读取操作之前，复位电路将数据总线对复位到预定的复位电压。 数据总线对的复位实际上不受数据总线对的分布电阻和寄生电容的影响，因为复位是在数据总线对上的多个位置进行的。
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公开(公告)号：US4807192A
公开(公告)日：1989-02-21
申请号：US90988
申请日：1987-08-31
CPC分类号： G11C7/1018 , G11C8/04
摘要： A memory device employing address multiplexing comprises a counter. An external address is initially set in the counter and a counter address value is incremented responsive to toggle of a column address strobe. The counted address value in the counter is supplied as an address signal directly to a column decoder or indirectly to the column decoder through an address buffer. The memory device may be provided with a switching logic circuit which switches the address bits in the counter depending on switching information so that it is possible to arbitrarily determine which address bits in the counter are to determine a nibble address.
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5.发明授权Dynamic random access memory having dummy word line for facilitating reset of row address latch 失效具有虚拟字线的动态随机存取存储器，以便于行地址锁存器的复位
公开(公告)号：US4989182A
公开(公告)日：1991-01-29
申请号：US254153
申请日：1988-10-06
IPC分类号： G11C11/407 , G11C8/14 , G11C8/18 , G11C11/408 , G11C11/409
CPC分类号： G11C8/18 , G11C11/408 , G11C8/14
摘要： A dynamic random access memory includes a dummy word line which has an electrical characteristic identical to that of an actual word line. The dummy word line is charged up and is then discharged as in case of the actual word line. A latched row address in a row address latch circuit is reset when the potential of the dummy word line becomes equal to a predetermined low potential due to the discharge operation for the dummy word line.
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公开(公告)号：US5537354A
公开(公告)日：1996-07-16
申请号：US357307
申请日：1994-12-14
申请人： Hirohiko Mochizuki , Yoshihiro Takemae , Yukinori Kodama , Makoto Yanagisawa , Hiroyoshi Tomita
发明人： Hirohiko Mochizuki , Yoshihiro Takemae , Yukinori Kodama , Makoto Yanagisawa , Hiroyoshi Tomita
IPC分类号： G11C11/401 , F02B75/02 , G11C7/10 , G11C11/407 , G11C11/409 , G11C13/00
CPC分类号： G11C7/1072 , F02B2075/025
摘要： A method of making an SDRAM (synchronous dynamic random access memory) into either a low-speed type or a high-speed type includes the steps of determining an electrical connection of a predetermined electrode of the SDRAM, and providing the predetermined electrode with a voltage level defined by the electrical connection, the voltage level determining whether the SDRAM is made into the low-speed type or the high speed type, wherein the low-speed type can carry out consecutive writing operations at a low clock rate for two addresses having the same row address, and the high-speed type can carry out simultaneous writing operations at a high clock rate for two addresses having the same row address and consecutive column addresses.
摘要翻译： 将SDRAM（同步动态随机存取存储器）制成低速型或高速型的方法包括以下步骤：确定SDRAM的预定电极的电连接，并为预定电极提供电压 由电气连接限定的电平，电压电平确定SDRAM是低速型还是高速型，其中低速类型可以以低时钟速率对具有 相同的行地址，并且高速类型可以以具有相同行地址和连续列地址的两个地址以高时钟速率执行同时写入操作。
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公开(公告)号：US5535169A
公开(公告)日：1996-07-09
申请号：US322564
申请日：1994-10-13
IPC分类号： G11C11/406 , G11C11/407 , G11C8/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device includes a plurality of banks each having a memory cell array and sense amplifiers, a data input/output circuit and an address circuit. A first part of the device receives control signals from an outside of the semiconductor memory device and generates a refresh signal therefrom. A second part generates bank select signals in response to the refresh signal, the bank select signals being used to select the plurality of banks. A third part receives the bank select signals and generating latch enable signals therefrom, the latch enable signals driving the sense amplifiers provided in the plurality of banks. A refresh operation is carried out by activating the sense amplifiers by using the latch enable signals.
摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元具有存储单元阵列和读出放大器，数据输入/输出电路和地址电路。 设备的第一部分从半导体存储器件的外部接收控制信号并从其产生刷新信号。 第二部分响应于刷新信号产生存储体选择信号，存储体选择信号用于选择多个存储体。 第三部分接收存储体选择信号并产生锁存使能信号，锁存器使能信号驱动设置在多个存储体中的读出放大器。 通过使用锁存使能信号来激活读出放大器来进行刷新操作。
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公开(公告)号：US5319607A
公开(公告)日：1994-06-07
申请号：US793970
申请日：1991-11-18
CPC分类号： G11C8/18
摘要： The present invention relates to a semiconductor unit including a delay circuit used for an address transition detecting circuit in a storage, wherein a change of an address is detected and, accordingly, an access address in a memory cell is altered. The present invention aims at ensuring extending an address signal even though that of a short pulse width is provided, and at outputting an address transition detection signal of a predetermined pulse width, thereby stabilizing the operation of the circuit and improving its reliability. The present invention includes a second address extending circuit having a complementary transistor circuit, a capacitor connected to the output part of the complementary transistor circuit, and a resistor serially connected between a pair of complementary transistors. A signal generating circuit for outputs an address transition detection signal in response to a non-inverted address signal, an inverted address signal, and output of the first and the second address extending circuits.
摘要翻译： 本发明涉及包括用于存储器中的地址转换检测电路的延迟电路的半导体单元，其中检测到地址的变化，因此改变了存储单元中的存取地址。 本发明的目的在于确保扩展地址信号，即使提供短脉冲宽度，并且输出预定脉冲宽度的地址转换检测信号，从而稳定电路的操作并提高其可靠性。 本发明包括具有互补晶体管电路的第二地址扩展电路，连接到互补晶体管电路的输出部分的电容器和串联连接在一对互补晶体管之间的电阻器。 一种信号发生电路，用于响应于非反相地址信号，反相地址信号和第一和第二地址扩展电路的输出输出地址转变检测信号。
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公开(公告)号：US5767712A
公开(公告)日：1998-06-16
申请号：US892066
申请日：1997-07-14
申请人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
发明人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , H03K3/356113 , H03K3/356156 , H03K5/133 , H03K5/1534 , H03K5/249
摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.
摘要翻译： 一种半导体器件包括：单脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟信号的周期时间 根据来自单触发脉冲发生电路的单触发脉冲输出，内部时钟发生电路，其基于由循环时间测量电路测量的周期时间和从单次脉冲发生电路输出的单次脉冲产生第二时钟信号; 射击脉冲发生电路。 第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟的周期时间获得特定时间 信号，以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。
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公开(公告)号：US06166992A
公开(公告)日：2000-12-26
申请号：US517338
申请日：2000-03-02
申请人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
发明人： Yoshihiro Takemae , Masao Taguchi , Yukinori Kodama , Makoto Yanagisawa , Takaaki Suzuki , Junji Ogawa , Atsushi Hatakeyama , Hirohiko Mochizuki , Hideaki Kawai
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , H03K3/356113 , H03K3/356156 , H03K5/133 , H03K5/1534 , H03K5/249
摘要： A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle-time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has a rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.
摘要翻译： 一种半导体器件包括：单触发脉冲发生电路，其在第一时钟信号的上升或下降定时产生具有预定脉冲宽度的单触发脉冲;周期时间测量电路，其测量第一时钟的周期时间 来自单触发脉冲发生电路输出的单触发脉冲的信号;内部时钟发生电路，其基于由周期时间测量电路测量的周期时间和从一个脉冲发生电路输出的单次脉冲产生第二时钟信号 -shot脉冲发生电路。 第二时钟信号具有与第一时钟信号相同的周期时间，并且具有比第一时钟信号高一个特定时间的上升或下降定时，并且通过减去第一时钟信号的周期时间来获得特定时间 时钟信号;以及数据输出电路，其在从第二时钟信号的上升或下降定时之后的预定延迟时间之后输出数据。
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