公开(公告)号：US4799197A

公开(公告)日：1989-01-17

申请号：US91795

申请日：1987-09-01

申请人： Yukinori Kodama ,  Hirohiko Mochizuki ,  Masao Nakano ,  Tsuyoshi Ohira ,  Hidenori Nomura

发明人： Yukinori Kodama ,  Hirohiko Mochizuki ,  Masao Nakano ,  Tsuyoshi Ohira ,  Hidenori Nomura

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4097 ,  G11C7/00 ,  G11C11/24

CPC分类号： G11C11/4097 ,  G11C11/4091 ,  G11C7/1006 ,  G11C7/18

摘要： A semiconductor memory device comprises a memory cell array comprising memory cells; a plurality of pairs of bit lines which are coupled to the memory cells and a data bus, each bit line being divided into at least two pairs of bit line parts; at least one sense amplifier provided between the pairs of bit line parts in each of the pairs of bit lines, for sensing a difference in potential between bit line parts in each pair, the sense amplifier being formed with complementary metal oxide semiconductor transistors; and at least a pair of transfer gates provided between a non-data bus side and a data bus side of the sense amplifier, the pair of transfer gates being held in an off-state when the sense amplifier is activated.

公开(公告)号：US4821232A

公开(公告)日：1989-04-11

申请号：US97556

申请日：1987-09-16

申请人： Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

发明人： Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/20 ,  G11C13/00 ,  G11C11/40

CPC分类号： G11C7/20 ,  G11C7/1048

摘要： A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells arranged in a matrix arrangement, a sense amplifier, operatively connected to the memory cell array, amplifying a signal read out from one of the memory cells and having a pair of output terminals for outputting a complementary signal, a pair of data buses for transferring the complementary signal, a transfer gate for connecting the pair of output terminals to the pair of data buses responsive to a read operation, a data output buffer connected to the pair of data buses for outputting an output signal, and a reset circuit for resetting the pair of data buses to a predetermined voltage before each read operation responsive to a reset clock signal. The reset circuit comprises a first circuit connected to the pair of data buses for connecting the pair of data buses to a common node responsive to the reset clock signal, and a second circuit connected between the common node and a ground voltage for shifting a potential at the common node to a voltage which is the predetermined voltage greater than the ground voltage.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括以矩阵布置的多个存储单元，读出放大器，可操作地连接到存储单元阵列，放大从一个存储单元读出的信号，并具有一对输出 用于输出互补信号的端子，用于传送互补信号的一对数据总线，用于响应于读取操作将一对输出端连接到该对数据总线的传输门，连接到该对数据的数据输出缓冲器 用于输出输出信号的总线;以及复位电路，用于响应于复位时钟信号在每次读取操作之前将该对数据总线复位到预定电压。 复位电路包括连接到该对数据总线的第一电路，用于响应于复位时钟信号将一对数据总线连接到公共节点，以及连接在公共节点和接地电压之间的第二电路， 该公共节点为大于接地电压的预定电压的电压。

公开(公告)号：US4870617A

公开(公告)日：1989-09-26

申请号：US97558

申请日：1987-09-16

申请人： Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

发明人： Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

IPC分类号： G11C11/409 ,  G11C5/06 ,  G11C7/10 ,  G11C11/401

CPC分类号： G11C5/063 ,  G11C7/1048

摘要： A semiconductor memory device comprises a plurality of reset circuits connected to a data bus pair at different locations. Before each read operation, the reset circuits reset the data bus pair to a predetermined reset voltage. The resetting of the data bus pair is virtually unaffected by the distributed resistances and parasitic capacitances of the data bus pair, since the resetting is carried out at a plurality of locations on the data bus pair.

摘要翻译： 半导体存储器件包括在不同位置连接到数据总线对的多个复位电路。 在每次读取操作之前，复位电路将数据总线对复位到预定的复位电压。 数据总线对的复位实际上不受数据总线对的分布电阻和寄生电容的影响，因为复位是在数据总线对上的多个位置进行的。

公开(公告)号：US4807192A

公开(公告)日：1989-02-21

申请号：US90988

申请日：1987-08-31

申请人： Masao Nakano ,  Hirohiko Mochizuki ,  Tsuyoshi Ohira ,  Yukinori Kodama ,  Hidenori Nomura

发明人： Masao Nakano ,  Hirohiko Mochizuki ,  Tsuyoshi Ohira ,  Yukinori Kodama ,  Hidenori Nomura

IPC分类号： G11C7/10 ,  G11C8/04 ,  G11C11/40 ,  G11C13/00

CPC分类号： G11C7/1018 ,  G11C8/04

摘要： A memory device employing address multiplexing comprises a counter. An external address is initially set in the counter and a counter address value is incremented responsive to toggle of a column address strobe. The counted address value in the counter is supplied as an address signal directly to a column decoder or indirectly to the column decoder through an address buffer. The memory device may be provided with a switching logic circuit which switches the address bits in the counter depending on switching information so that it is possible to arbitrarily determine which address bits in the counter are to determine a nibble address.

公开(公告)号：US4989182A

公开(公告)日：1991-01-29

申请号：US254153

申请日：1988-10-06

申请人： Hirohiko Mochizuki ,  Tsuyoshi Ohira ,  Yukinori Kodama ,  Meiko Kobayashi ,  Takaaki Furuyama

发明人： Hirohiko Mochizuki ,  Tsuyoshi Ohira ,  Yukinori Kodama ,  Meiko Kobayashi ,  Takaaki Furuyama

IPC分类号： G11C11/407 ,  G11C8/14 ,  G11C8/18 ,  G11C11/408 ,  G11C11/409

CPC分类号： G11C8/18 ,  G11C11/408 ,  G11C8/14

摘要： A dynamic random access memory includes a dummy word line which has an electrical characteristic identical to that of an actual word line. The dummy word line is charged up and is then discharged as in case of the actual word line. A latched row address in a row address latch circuit is reset when the potential of the dummy word line becomes equal to a predetermined low potential due to the discharge operation for the dummy word line.

公开(公告)号：US4806795A

公开(公告)日：1989-02-21

申请号：US97557

申请日：1987-09-16

申请人： Masao Nakano ,  Tsuyoshi Ohira ,  Hidenori Nomura

发明人： Masao Nakano ,  Tsuyoshi Ohira ,  Hidenori Nomura

IPC分类号： H01L27/08 ,  H01L21/8238 ,  H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H03K19/096

CPC分类号： H03K17/6872

摘要： A transfer gate circuit including a first MIS transistor which transmits an input signal supplied from an input side thereof to an output side thereof in accordance with a control signal supplied to a gate of the first MIS transistor; an inverter circuit connected between power supply lines which inverts the potential of the transmitted input signal; and an output level guarantee circuit comprising second and third MIS transistors which have conductivity type opposite to that of the first MIS transistor and are connected in series between one of the power supply lines and the output side, an output signal of the inverter circuit being supplied to a gate of the second MIS transistor, an inverted signal of the control signal supplied to the gate of the first MIS transistor being supplied to a gate of the third MIS transistor.

摘要翻译： 一种传输门电路，包括：第一MIS晶体管，其根据提供给第一MIS晶体管的栅极的控制信号将从其输入侧提供的输入信号传输到其输出侧; 连接在电源线之间的逆变器电路，其反转所发送的输入信号的电位; 以及输出电平保证电路，包括第二和第三MIS晶体管，其具有与第一MIS晶体管的导电类型相反的导电类型，并且串联连接在一个电源线和输出侧之间，反相器电路的输出信号被提供 到第二MIS晶体管的栅极，提供给第一MIS晶体管的栅极的控制信号的反相信号被提供给第三MIS晶体管的栅极。

公开(公告)号：US4484312A

公开(公告)日：1984-11-20

申请号：US392077

申请日：1982-06-25

申请人： Tomio Nakano ,  Masao Nakano ,  Yoshihiro Takemae ,  Norihisa Tsuge ,  Tsuyoshi Ohira

发明人： Tomio Nakano ,  Masao Nakano ,  Yoshihiro Takemae ,  Norihisa Tsuge ,  Tsuyoshi Ohira

IPC分类号： G11C11/401 ,  G11C11/4099 ,  G11C11/40

CPC分类号： G11C11/4099

摘要： A dynamic random access memory device which comprises one-transistor, one-capacitor-type memory cells (C.sub.00 .about.C.sub.127,127) in rows and columns and dummy cells (DC.sub.20 '.about.DC.sub.2,127 ', DC.sub.20 ".about.DC.sub.2,127 ", DC.sub.20 "'.about.DC.sub.2,127 "') in rows. The capacitors (C.sub.d) of the dummy cells are charged to a high power supply potential (V.sub.CC) by one or more charging transistors (Q.sub.A or Q.sub.A ') clocked by a reset clock signal (.phi..sub.R). The capacitors (C.sub.d) of the dummy cells are discharged to a low power supply potential (V.sub.SS) by one or more transistors (Q.sub.B or Q.sub.B ') clocked by an operation clock signal (.phi..sub.WL) having a potential lower than the high power supply potential (V.sub.CC).

摘要翻译： 一种动态随机存取存储器件，其包括行和列中的单晶体管，单电容器型存储单元（C00 DIFFERENCE C127,127）和虚设单元（DC20'DIFFERENCE DC2,127'，DC20“DIFFERENCE DC2,127” '，DC20'''DIFFERENCE DC2,127'''）。 虚拟单元的电容器（Cd）通过由复位时钟信号（phi R）计时的一个或多个充电晶体管（QA或QA'）充电到高电源电位（VCC）。 虚拟单元的电容器（Cd）由一个或多个晶体管（QB或QB'）放电到低电源电位（VSS），该晶体管（QB或QB'）由具有低于高电源电位的电位的操作时钟信号（phi WL） 电位（VCC）。

公开(公告)号：US4450515A

公开(公告)日：1984-05-22

申请号：US388194

申请日：1982-06-14

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Norihisa Tsuge ,  Tsuyoshi Ohira

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Norihisa Tsuge ,  Tsuyoshi Ohira

IPC分类号： H01L27/04 ,  G05F3/20 ,  G11C11/407 ,  H01L21/822 ,  H03K17/06 ,  H03K19/00 ,  H03K19/094 ,  H02M3/18 ,  H03K3/01

CPC分类号： G05F3/205

摘要： A bias-voltage generator suitable for measuring a substrate leakage current is disclosed. The bias-voltage generator comprises of an oscillator, a charge-pumping circuit which is driven by the oscillator via a pumping capacitor, and a charge-pumping switch. The charge-pumping switch is connected in series with the charge-pumping circuit. The charge-pumping switch cooperates with an external electrode for controlling the ON or OFF condition of the charge pumping circuit. The charge-pumping switch is turned OFF by the external electrode becoming a floating state and a resistor employed to ensure the charge pumping switch is inoperable after the above-mentioned measurement is completed and the circuit is shipped from the factory.

摘要翻译： 公开了一种适用于测量衬底漏电流的偏置电压发生器。 偏置电压发生器包括振荡器，由振荡器经由泵浦电容器驱动的电荷泵浦电路和电荷泵浦开关。 电荷泵开关与充电电路串联。 电荷泵开关与外部电极配合，用于控制电荷泵送电路的导通或关断状态。 通过外部电极变为浮置状态，电荷泵浦开关被切断，并且在上述测量完成并且电路从工厂出货之后用于确保电荷泵开关不可操作的电阻器。

公开(公告)号：US09183699B2

公开(公告)日：2015-11-10

申请号：US12251777

申请日：2008-10-15

申请人： Kenichi Fujimori ,  Arata Ajiro ,  Tsuyoshi Ohira

发明人： Kenichi Fujimori ,  Arata Ajiro ,  Tsuyoshi Ohira

IPC分类号： A63F13/00 ,  A63F9/24 ,  G07F17/32 ,  A63F13/40 ,  A63F13/30

CPC分类号： G07F17/3223 ,  A63F13/10 ,  A63F13/12 ,  G07F17/3211 ,  G07F17/3258 ,  G07F17/3272

摘要： A gaming system of the present invention includes: a plurality of gaming machines; and a common display device connected to the gaming machines, each of the gaming machines, comprising: a display device for displaying a plurality of symbols; a controller, which performs processes of: (a) executing a base game in which symbols arranged on the display device are rearranged after a gaming medium has been betted, and thereafter a payment is made in accordance with the rearranged symbols; (b) counting number of times of executing the base game; (c) causing the display device to display a countdown effect image stored in a memory, while the counted number of times of executing the base game reaches a second predetermined value after reaching a first predetermined value; and (d) transferring the base game to a free game executed without betting a gaming medium, in a case where the number of times of executing the base game reaches the second predetermined value; and a communication interface for notifying to the common display the controller-counted number of times of executing the base game, the common display device, comprising: a communication interface for receiving notification from each of the gaming machines; a memory for storing a countdown effect image for each of the gaming machines; and a controller, which performs processes of: (a′) judging whether or not there exist a plurality of gaming machines at which number of times of executing the base game reaches the first predetermined value, based upon the number of times of executing the base game, which is notified from each of the gaming machine; and (b′) preferentially displaying a countdown effect image for a gaming machine with a smaller number of times of executing the base game, which is to be executed until a transfer to the free game.

摘要翻译： 本发明的游戏系统包括：多个游戏机; 以及连接到游戏机的通用显示装置，每个游戏机包括：显示装置，用于显示多个符号; 执行以下处理的控制器：（a）执行基本游戏，其中在游戏介质被投注之后重排布置在显示设备上的符号，然后根据重新排列的符号进行支付; （b）计算执行基本游戏的次数; （c）使显示装置显示存储在存储器中的倒计时效果图像，同时执行基本游戏的计数次数在达到第一预定值之后达到第二预定值; 以及（d）在执行基本游戏的次数达到第二预定值的情况下，将基本游戏转移到执行而不下注游戏媒体的免费游戏; 以及通信接口，用于向所述公共显示器通知所述控制器计数的执行所述基本游戏的次数，所述公共显示装置包括：通信接口，用于从每个所述游戏机接收通知; 用于存储每个游戏机的倒计时效果图像的存储器; 以及控制器，其执行以下处理：（a'）基于执行基数的次数判断是否存在执行基本游戏的次数达到第一预定值的多个游戏机 游戏，从每个游戏机通知; 和（b'）优先显示具有较少执行基本游戏次数的游戏机的倒计时效果图像，该游戏机将被执行直到转移到免费游戏。

公开(公告)号：US20090239628A1

公开(公告)日：2009-09-24

申请号：US12251777

申请日：2008-10-15

申请人： Kenichi Fujimori ,  Arata Ajiro ,  Tsuyoshi Ohira

发明人： Kenichi Fujimori ,  Arata Ajiro ,  Tsuyoshi Ohira

IPC分类号： A63F9/24

CPC分类号： G07F17/3223 ,  A63F13/10 ,  A63F13/12 ,  G07F17/3211 ,  G07F17/3258 ,  G07F17/3272

摘要： A gaming system of the present invention includes: a plurality of gaming machines; and a common display device connected to the gaming machines, each of the gaming machines, comprising: a display device for displaying a plurality of symbols; a controller, which performs processes of: (a) executing a base game in which symbols arranged on the display device are rearranged after a gaming medium has been betted, and thereafter a payment is made in accordance with the rearranged symbols; (b) counting number of times of executing the base game; (c) causing the display device to display a countdown effect image stored in a memory, while the counted number of times of executing the base game reaches a second predetermined value after reaching a first predetermined value; and (d) transferring the base game to a free game executed without betting a gaming medium, in a case where the number of times of executing the base game reaches the second predetermined value; and a communication interface for notifying to the common display the controller-counted number of times of executing the base game, the common display device, comprising: a communication interface for receiving notification from each of the gaming machines; a memory for storing a countdown effect image for each of the gaming machines; and a controller, which performs processes of: (a′) judging whether or not there exist a plurality of gaming machines at which number of times of executing the base game reaches the first predetermined value, based upon the number of times of executing the base game, which is notified from each of the gaming machine; and (b′) preferentially displaying a countdown effect image for a gaming machine with a smaller number of times of executing the base game, which is to be executed until a transfer to the free game.

摘要翻译： 本发明的游戏系统包括：多个游戏机; 以及连接到游戏机的通用显示装置，每个游戏机包括：显示装置，用于显示多个符号; 执行以下处理的控制器：（a）执行基本游戏，其中在游戏介质被投注之后重排布置在显示设备上的符号，然后根据重新排列的符号进行支付; （b）计算执行基本游戏的次数; （c）使显示装置显示存储在存储器中的倒计时效果图像，同时执行基本游戏的计数次数在达到第一预定值之后达到第二预定值; 以及（d）在执行基本游戏的次数达到第二预定值的情况下，将基本游戏转移到执行而不下注游戏媒体的免费游戏; 以及通信接口，用于向所述公共显示器通知所述控制器计数的执行所述基本游戏的次数，所述公共显示装置包括：通信接口，用于从每个所述游戏机接收通知; 用于存储每个游戏机的倒计时效果图像的存储器; 以及控制器，其执行以下处理：（a'）基于执行基数的次数判断是否存在执行基本游戏的次数达到第一预定值的多个游戏机 游戏，从每个游戏机通知; 和（b'）优先显示具有较少执行基本游戏次数的游戏机的倒计时效果图像，该游戏机将被执行直到转移到免费游戏。