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公开(公告)号：US4821232A
公开(公告)日：1989-04-11
申请号：US97556
申请日：1987-09-16
IPC分类号： G11C11/409 , G11C7/10 , G11C7/20 , G11C13/00 , G11C11/40
CPC分类号： G11C7/20 , G11C7/1048
摘要： A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells arranged in a matrix arrangement, a sense amplifier, operatively connected to the memory cell array, amplifying a signal read out from one of the memory cells and having a pair of output terminals for outputting a complementary signal, a pair of data buses for transferring the complementary signal, a transfer gate for connecting the pair of output terminals to the pair of data buses responsive to a read operation, a data output buffer connected to the pair of data buses for outputting an output signal, and a reset circuit for resetting the pair of data buses to a predetermined voltage before each read operation responsive to a reset clock signal. The reset circuit comprises a first circuit connected to the pair of data buses for connecting the pair of data buses to a common node responsive to the reset clock signal, and a second circuit connected between the common node and a ground voltage for shifting a potential at the common node to a voltage which is the predetermined voltage greater than the ground voltage.
摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括以矩阵布置的多个存储单元，读出放大器，可操作地连接到存储单元阵列，放大从一个存储单元读出的信号，并具有一对输出 用于输出互补信号的端子，用于传送互补信号的一对数据总线，用于响应于读取操作将一对输出端连接到该对数据总线的传输门，连接到该对数据的数据输出缓冲器 用于输出输出信号的总线;以及复位电路，用于响应于复位时钟信号在每次读取操作之前将该对数据总线复位到预定电压。 复位电路包括连接到该对数据总线的第一电路，用于响应于复位时钟信号将一对数据总线连接到公共节点，以及连接在公共节点和接地电压之间的第二电路， 该公共节点为大于接地电压的预定电压的电压。
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公开(公告)号：US4799197A
公开(公告)日：1989-01-17
申请号：US91795
申请日：1987-09-01
IPC分类号： G11C11/401 , G11C7/10 , G11C7/18 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C7/00 , G11C11/24
CPC分类号： G11C11/4097 , G11C11/4091 , G11C7/1006 , G11C7/18
摘要： A semiconductor memory device comprises a memory cell array comprising memory cells; a plurality of pairs of bit lines which are coupled to the memory cells and a data bus, each bit line being divided into at least two pairs of bit line parts; at least one sense amplifier provided between the pairs of bit line parts in each of the pairs of bit lines, for sensing a difference in potential between bit line parts in each pair, the sense amplifier being formed with complementary metal oxide semiconductor transistors; and at least a pair of transfer gates provided between a non-data bus side and a data bus side of the sense amplifier, the pair of transfer gates being held in an off-state when the sense amplifier is activated.
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公开(公告)号：US4870617A
公开(公告)日：1989-09-26
申请号：US97558
申请日：1987-09-16
IPC分类号： G11C11/409 , G11C5/06 , G11C7/10 , G11C11/401
CPC分类号： G11C5/063 , G11C7/1048
摘要： A semiconductor memory device comprises a plurality of reset circuits connected to a data bus pair at different locations. Before each read operation, the reset circuits reset the data bus pair to a predetermined reset voltage. The resetting of the data bus pair is virtually unaffected by the distributed resistances and parasitic capacitances of the data bus pair, since the resetting is carried out at a plurality of locations on the data bus pair.
摘要翻译： 半导体存储器件包括在不同位置连接到数据总线对的多个复位电路。 在每次读取操作之前，复位电路将数据总线对复位到预定的复位电压。 数据总线对的复位实际上不受数据总线对的分布电阻和寄生电容的影响，因为复位是在数据总线对上的多个位置进行的。
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公开(公告)号：US4807192A
公开(公告)日：1989-02-21
申请号：US90988
申请日：1987-08-31
CPC分类号： G11C7/1018 , G11C8/04
摘要： A memory device employing address multiplexing comprises a counter. An external address is initially set in the counter and a counter address value is incremented responsive to toggle of a column address strobe. The counted address value in the counter is supplied as an address signal directly to a column decoder or indirectly to the column decoder through an address buffer. The memory device may be provided with a switching logic circuit which switches the address bits in the counter depending on switching information so that it is possible to arbitrarily determine which address bits in the counter are to determine a nibble address.
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公开(公告)号：US4806795A
公开(公告)日：1989-02-21
申请号：US97557
申请日：1987-09-16
申请人： Masao Nakano , Tsuyoshi Ohira , Hidenori Nomura
发明人： Masao Nakano , Tsuyoshi Ohira , Hidenori Nomura
IPC分类号： H01L27/08 , H01L21/8238 , H01L27/092 , H03K17/687 , H03K17/16 , H03K19/096
CPC分类号： H03K17/6872
摘要： A transfer gate circuit including a first MIS transistor which transmits an input signal supplied from an input side thereof to an output side thereof in accordance with a control signal supplied to a gate of the first MIS transistor; an inverter circuit connected between power supply lines which inverts the potential of the transmitted input signal; and an output level guarantee circuit comprising second and third MIS transistors which have conductivity type opposite to that of the first MIS transistor and are connected in series between one of the power supply lines and the output side, an output signal of the inverter circuit being supplied to a gate of the second MIS transistor, an inverted signal of the control signal supplied to the gate of the first MIS transistor being supplied to a gate of the third MIS transistor.
摘要翻译： 一种传输门电路，包括：第一MIS晶体管，其根据提供给第一MIS晶体管的栅极的控制信号将从其输入侧提供的输入信号传输到其输出侧; 连接在电源线之间的逆变器电路，其反转所发送的输入信号的电位; 以及输出电平保证电路，包括第二和第三MIS晶体管，其具有与第一MIS晶体管的导电类型相反的导电类型，并且串联连接在一个电源线和输出侧之间，反相器电路的输出信号被提供 到第二MIS晶体管的栅极，提供给第一MIS晶体管的栅极的控制信号的反相信号被提供给第三MIS晶体管的栅极。
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公开(公告)号：US4413272A
公开(公告)日：1983-11-01
申请号：US183734
申请日：1980-09-03
IPC分类号： G11C17/06 , G11C17/00 , G11C17/14 , G11C17/16 , H01L23/50 , H01L23/52 , H01L23/525 , H01L23/62
CPC分类号： G11C17/16 , H01L23/5256 , H01L23/62 , H01L2924/0002
摘要： A semiconductor memory device has fuses coated with a protecting layer. The protecting layer is selectively etched to open windows so as to expose narrow center portions of the fuses. After the opening of the center windows, the fusing operation of the fuses is carried out to open a gap in the center window portion of the fuse material. In a preferred embodiment, another protective layer is then added to fill the gaps in the blown fuses.
摘要翻译： 半导体存储器件具有涂覆有保护层的保险丝。 选择性地蚀刻保护层以打开窗口，以便露出保险丝的中心部分。 在中心窗口打开之后，执行保险丝的熔合操作以在熔断体的中心窗部分中打开间隙。 在优选实施例中，然后添加另一保护层以填充熔断保险丝中的间隙。
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公开(公告)号：US4382194A
公开(公告)日：1983-05-03
申请号：US213398
申请日：1980-12-05
申请人： Masao Nakano , Fumio Baba , Hirohiko Mochizuki
发明人： Masao Nakano , Fumio Baba , Hirohiko Mochizuki
IPC分类号： H03K19/0185 , G11C5/14 , G11C11/4076 , G11C11/408 , H02M3/07 , H03K5/00 , H03K5/02 , H03K19/00 , H03K19/017 , H03K19/096 , H03K4/24 , H03K5/01
CPC分类号： H02M3/07 , G11C11/4076 , G11C11/4085 , G11C5/145 , H03K19/00 , H03K19/01707 , H03K19/01728 , H03K19/096 , H03K5/00
摘要： A boosting circuit boosts a voltage of a load capacitor which is charged by a specific voltage. The boosting circuit comprises a boosting capacitor one end of which is connected to receive a clock signal, a charging circuit for charging the boosting capacitor, a gate circuit provided between the load capacitor and the other end of the boosting capacitor, and a gate control circuit for opening the gate circuit upon discharging of the charge of the boosting, that is controlled by the clock signal, to the load capacitor and for closing the gate circuit during discharging of the load capacitor. The charging circuit is provided separately from a circuit for supplying the specific voltage. The charges of the boosting capacitor under the control of the clock signal flow through the gate circuit to the load capacitor.
摘要翻译： 升压电路提高由特定电压充电的负载电容器的电压。 升压电路包括一个升压电容器，其一端连接以接收时钟信号，用于对升压电容器充电的充电电路，设置在负载电容器和升压电容器的另一端之间的门电路，以及栅极控制电路 用于在由时钟信号控制的放电电荷放电到负载电容器并且在负载电容器放电期间闭合栅极电路时打开门电路。 充电电路与用于提供特定电压的电路分开设置。 在时钟信号控制下的升压电容器的电荷通过栅极电路流到负载电容器。
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8.发明授权Semiconductor memory device having a dummy cell resetting the bit lines to a reset potential that is based on data read in a previous read data 失效具有虚设单元的半导体存储器件，其将位线复位为基于在先前读取数据中读取的数据的复位电位
公开(公告)号：US6154405A
公开(公告)日：2000-11-28
申请号：US924315
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Hirohiko Mochizuki , Hiroyoshi Tomita , Yasurou Matsuzaki , Tadao Aikawa
发明人： Yoshihiro Takemae , Masao Taguchi , Masao Nakano , Hirohiko Mochizuki , Hiroyoshi Tomita , Yasurou Matsuzaki , Tadao Aikawa
IPC分类号： G11C11/409 , G11C7/10 , G11C7/12 , G11C11/401 , G11C11/407 , G11C11/4096 , G11C7/02
CPC分类号： G11C11/4096 , G11C7/1048 , G11C7/12
摘要： A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.
摘要翻译： 半导体存储器件包括存储器单元，连接到存储器单元的字线，连接到存储器单元的位线，以及基于在先前读取周期中读取的数据将位线复位到复位电位的第一电路。
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公开(公告)号：US6028816A
公开(公告)日：2000-02-22
申请号：US924705
申请日：1997-09-05
申请人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
发明人： Yoshihiro Takemae , Masao Taguchi , Yasurou Matsuzaki , Hiroyoshi Tomita , Hirohiko Mochizuki , Atsushi Hatakeyama , Yoshinori Okajima , Masao Nakano
IPC分类号： G06F13/42 , G06F1/10 , G06F1/12 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/4093 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081 , H04L7/00 , G11C8/00
CPC分类号： H03L7/0805 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , H03K5/133 , H03K5/135 , H03L7/00 , H03L7/0814 , G11C2207/108
摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.
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公开(公告)号：US4392211A
公开(公告)日：1983-07-05
申请号：US243927
申请日：1981-02-20
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/844
摘要： A semiconductor memory device wherein a redundancy memory cell array incorporated with main memory cell matrixes is disclosed. Memory cells of the main memory cell matrixes are selected by first and third decoders while memory cells of the redundancy memory cell array are selected by second and third decoders. When the redundancy memory cell array is selected by the second decoder, the transmission of a clock signal to the first decoders is stopped by a switching circuit.
摘要翻译： PCT No.PCT / JP80 / 00143 Sec。 371日期：1981年2月25日 102（e）日期1981年2月20日PCT归档1980年6月24日PCT公布。 出版物WO81 / 日本1981年1月8日。一种半导体存储器件，其中并入有主存储单元矩阵的冗余存储单元阵列被公开。 主存储单元矩阵的存储单元由第一和第三解码器选择，而冗余存储单元阵列的存储单元由第二和第三解码器选择。 当由第二解码器选择冗余存储单元阵列时，通过切换电路停止向第一解码器传输时钟信号。
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