公开(公告)号：US10886160B2

公开(公告)日：2021-01-05

申请号：US16188368

申请日：2018-11-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Alexei Sadovnikov ,  Scott Kelly Montgomery

IPC: H01L27/088 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/74 ,  H01L29/10 ,  H01L29/423

Abstract: An electronic device, e.g. an integrated circuit, includes a semiconductor substrate having a top surface and an area of the semiconductor substrate surrounded by inner and outer trench rings. The inner trench ring includes a first dielectric liner that extends from the substrate surface to a bottom of the inner trench ring, the first dielectric liner electrically isolating an interior region of the inner trench ring from the semiconductor substrate. The outer trench ring surrounds the inner trench ring and includes a second dielectric liner that extends from the substrate surface to a bottom of the outer trench ring. The second dielectric liner includes an opening at a bottom of the outer trench ring, the opening providing a path between an interior region of the outer trench ring and the semiconductor substrate.

公开(公告)号：US20200006549A1

公开(公告)日：2020-01-02

申请号：US16021601

申请日：2018-06-28

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Andrew Derek Strachan ,  Henry Litzmann Edwards ,  Dhanoop Varghese ,  Xiaoju Wu ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/266 ,  H01L21/265

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.

公开(公告)号：US10269895B2

公开(公告)日：2019-04-23

申请号：US15647493

申请日：2017-07-12

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/082 ,  H01L29/04 ,  H01L29/16 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L29/08 ,  H01L21/8228 ,  H01L29/10 ,  H01L29/732 ,  H01L21/266

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

公开(公告)号：US20190103471A1

公开(公告)日：2019-04-04

申请号：US15720616

申请日：2017-09-29

Applicant: Texas Instruments Incorporated

Inventor： Umamaheswari Aghoram ,  Pushpa Mahalingam ,  Alexei Sadovnikov ,  Eugene C. Davis

IPC: H01L29/423 ,  H01L29/221 ,  H01L21/02

CPC classification number: H01L29/42336 ,  H01L21/02439 ,  H01L21/02502 ,  H01L21/761 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/221 ,  H01L29/402 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure is formed between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon dioxide.

公开(公告)号：US09905428B2

公开(公告)日：2018-02-27

申请号：US14930633

申请日：2015-11-02

Applicant: Texas Instruments Incorporated

Inventor： Andrew D Strachan ,  Alexei Sadovnikov ,  Christopher Boguslaw Kocon

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L21/28114 ,  H01L21/28158 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7831 ,  H01L29/7835

Abstract: A semiconductor device includes a split-gate lateral extended drain MOS transistor, which includes a first gate and a second gate laterally adjacent to the first gate. The first gate is laterally separated from the second gate by a gap of 10 nanometers to 250 nanometers. The first gate extends at least partially over the body, and the second gate extends at least partially over a drain drift region. The drain drift region abuts the body at a top surface of the substrate. A boundary between the drain drift region and the body at the top surface of the substrate is located under at least one of the first gate, the second gate and the gap between the first gate and the second gate. The second gate may be coupled to a gate bias voltage node or a gate signal node.

公开(公告)号：US09786665B1

公开(公告)日：2017-10-10

申请号：US15238198

申请日：2016-08-16

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Binghua Hu ,  Alexei Sadovnikov ,  Guru Mathur

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/76229 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0615 ,  H01L29/0649

Abstract: A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.

公开(公告)号：US09741790B2

公开(公告)日：2017-08-22

申请号：US15098452

申请日：2016-04-14

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/082 ,  H01L29/04 ,  H01L29/16 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L29/08 ,  H01L21/8228 ,  H01L29/10 ,  H01L29/732 ,  H01L21/266

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/8228 ,  H01L21/82285 ,  H01L27/082 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/732

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

公开(公告)号：US20160141363A1

公开(公告)日：2016-05-19

申请号：US14540105

申请日：2014-11-13

Applicant: Texas Instruments Incorporated

Inventor： Natalia Lavrovskaya ,  Alexei Sadovnikov

IPC: H01L29/08 ,  H01L27/06 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0692 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/735

Abstract: In a lateral BJT formed using a BiCMOS process, the collector-to-emitter breakdown voltage (BVCEO) and BJT's gain, are improved by forming a graded collector contact region with lower doping levels toward the base contact.

Abstract translation: 在使用BiCMOS工艺形成的横向BJT中，通过形成具有较低掺杂浓度的渐变集电极接触区域来朝向基极接触而提高集电极至发射极击穿电压（BVCEO）和BJT的增益。

公开(公告)号：US20150287716A1

公开(公告)日：2015-10-08

申请号：US14245099

申请日：2014-04-04

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. Babcock ,  Alexei Sadovnikov

IPC: H01L27/082 ,  H01L29/04 ,  H01L29/16 ,  H01L21/265 ,  H01L21/8228 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L29/08 ,  H01L29/06 ,  H01L21/266

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/8228 ,  H01L21/82285 ,  H01L27/082 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/732

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

Abstract translation: 公开了在标准体硅集成电路中形成的互补高电压双极晶体管。 在一个公开的实施例中，集电极区域形成在外延硅层中。 基极区域和发射极设置在集电极区域上。 通过将供体杂质注入用于PNP晶体管的p衬底中并在沉积集电极外延区之前将受体杂质注入到NPN晶体管的p衬底中，在集电极区域形成n型区域。 在工艺流程中，这些n型和p型区域分别通过深n +和p +阱连接到管芯的顶部。 然后将n型阱耦合到VCC，而p型阱耦合到GND，提供PNP和NPN集电极区域的横向耗尽部分，并因此增加其BV。

公开(公告)号：US20250040179A1

公开(公告)日：2025-01-30

申请号：US18361880

申请日：2023-07-30

Applicant: Texas Instruments Incorporated

Inventor： Pushpa Mahalingam ,  Alexei Sadovnikov ,  Nick Dunteman ,  Ryan Rust

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: Semiconductor devices including a high-k field relief dielectric structure are described. The microelectronic device comprises a substrate including a body region and a drain drift region on the substrate, a gate dielectric layer extending over the body region and the drift region, a drain drift trench is formed by removal of silicon dioxide from a LOCOS silicon region, a high-k field relief dielectric structure laterally abutting the gate dielectric layer at a location in the drift region, and a gate electrode on the gate dielectric layer and the field relief dielectric layer. Increasing the dielectric constant of the field relief dielectric structure may improve channel hot carrier performance, improve breakdown voltage, and reduce the specific on resistance. A drain drift trench formed in a trench left after removal of silicon dioxide in a LOCOS region provides improved trench depth uniformity.