公开(公告)号：US12026521B2

公开(公告)日：2024-07-02

申请号：US17521378

申请日：2021-11-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Edward Wentroble ,  Anant Shankar Kamath ,  Rakesh Hariharan ,  Prajwala P ,  Suzanne Mary Vining

IPC: G06F13/00 ,  G06F1/3215 ,  G06F9/4401 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/4411 ,  G06F1/3215 ,  G06F13/382 ,  G06F13/4282 ,  G06F2213/0042

Abstract: A serial bus repeater includes first and second ports adapted to be coupled to respective devices. A first termination resistor network couples to the first port. A second termination resistor network couples to the second port. A squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. A first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.

公开(公告)号：US11869933B2

公开(公告)日：2024-01-09

申请号：US17398292

申请日：2021-08-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/761 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L21/265

CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/05 ,  H01L27/0676 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/48463

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

公开(公告)号：US11669475B2

公开(公告)日：2023-06-06

申请号：US17246137

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar Kamath ,  Rakesh Hariharan ,  Mark Edward Wentroble

IPC: G06F13/38 ,  H03K5/24 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/385 ,  G06F13/4072 ,  G06F13/4221 ,  H03K5/2472

Abstract: An isolating repeater and corresponding method for Universal Serial Bus (USB) communications. The isolating repeater includes, on either side of a galvanic isolation barrier, front end circuitry coupled to a pair of external terminals, a full speed (FS) transceiver adapted to drive and receive signals over one or more FS isolation channels, and a high speed (HS) transceiver adapted to drive signals over a one HS isolation channel and receive signals over another HS isolation channel. The front end circuitry encodes received signals corresponding to HS data into two-state signals for transmission over one HS isolation channel, and encodes received signals corresponding to HS signaling into two-state signals for transmission over one or more of the FS isolation channels. The front end circuitry on the other side of the isolation barrier decodes the two-state signals received over the one or more FS isolation channels and the two-state signals received over the HS isolation channel for transmission at its external terminals.

公开(公告)号：US11630797B2

公开(公告)日：2023-04-18

申请号：US17341089

申请日：2021-06-07

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar Kamath ,  Rakesh Hariharan ,  Vivekkumar Ramanlal Vadodariya ,  Soumi Paul ,  Mayank Garg

IPC: G06F13/42 ,  G06F1/3215 ,  G06F13/38

Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.

公开(公告)号：US11563462B1

公开(公告)日：2023-01-24

申请号：US17382499

申请日：2021-07-22

Applicant: Texas Instruments Incorporated

Inventor： Srijan Rastogi ,  Mayank Garg ,  Anant Shankar Kamath

IPC: H04B3/36 ,  H03F3/45

Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

公开(公告)号：US11443889B2

公开(公告)日：2022-09-13

申请号：US16903618

申请日：2020-06-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dushmantha Bandara Rajapaksha ,  Roland Sperlich ,  Anant Shankar Kamath ,  Vijayalakshmi Devarajan ,  Wesley Ray

IPC: H02M3/155 ,  H01F27/28 ,  H04L13/02 ,  H02M1/42

Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

公开(公告)号：US10186576B2

公开(公告)日：2019-01-22

申请号：US15714682

申请日：2017-09-25

Applicant: Texas Instruments Incorporated

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L21/76 ,  H01L23/522 ,  H01L27/06 ,  H01L49/02 ,  H01L21/761 ,  H01L21/265 ,  H01L23/528 ,  H01L23/00

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include methods of forming an integrated circuit including an isolator structure. The isolator structure includes parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator

公开(公告)号：US09806148B2

公开(公告)日：2017-10-31

申请号：US14680211

申请日：2015-04-07

Applicant: Texas Instruments Incorporated

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/761 ,  H01L49/02 ,  H01L21/265 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/05 ,  H01L27/0676 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/48463

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

公开(公告)号：US09698728B2

公开(公告)日：2017-07-04

申请号：US14103386

申请日：2013-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anant Shankar Kamath ,  Sreeram N S

IPC: H04L25/02 ,  H03D3/00

CPC classification number: H03D3/00 ,  H04L25/0268

Abstract: Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an isolation element, input circuit, and output circuit. The isolation element includes at least one input node and at least one output node, the input circuit is electronically coupled to the input node and generates modulated differential data signals based on modulating the input data signal on a carrier signal. The input circuit operates using a first supply voltage with respect to a first ground. The output circuit is electronically coupled to the output node to receive the modulated differential data signals, operates using a second supply voltage with respect to a second ground and includes a frequency-shift keying demodulator configured to generate a demodulated data signal in response to detection of presence of the carrier signal. The output circuit further generates an output data signal.

公开(公告)号：US09455721B2

公开(公告)日：2016-09-27

申请号：US14588293

申请日：2014-12-31

Applicant: Texas Instruments Incorporated

Inventor： Divyasree J. ,  Anant Shankar Kamath

IPC: H03L7/06 ,  H03K3/03 ,  H03K4/06 ,  H03L7/00

CPC classification number: H03L7/06 ,  H03K3/0231 ,  H03K3/0315 ,  H03K3/84 ,  H03K4/06 ,  H03L7/00

Abstract: An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an FLL-controlled frequency fOSC. The FLL control loop includes a switched capacitor resistor divider that converts fOSC to a resistance, generating an FLL feedback voltage Vfosc used to generate a loop control signal OSC_cntrl input to the oscillator. In response, the oscillator frequency locks FLL_clk to fosc. In an example implementation, the FLL oscillator/clock operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.

Abstract translation: FLL（锁频环）振荡器/时钟发生器包括一个自由振荡器（例如环形振荡器），并产生具有FLL控制频率fOSC的FLL_clk。 FLL控制回路包括将fOSC转换为电阻的开关电容电阻分压器，产生用于产生输入到振荡器的回路控制信号OSC_cntrl的FLL反馈电压Vfosc。 作为响应，振荡器频率将FLL_clk锁定到fosc。 在示例实现中，FLL振荡器/时钟以扩频时钟（SSC）工作，该扩频频谱时钟（SSC）基于产生为RC松弛振荡器的负反馈的截断RC转换电压提供三角形SSC调制，基于产生的切换跳闸阈值电压进行截断 对RC松弛振荡器的正反馈。