公开(公告)号：US11205578B2

公开(公告)日：2021-12-21

申请号：US16161920

申请日：2018-10-16

Applicant: Texas Instruments Incorporated

Inventor： Brian K. Kirkpatrick ,  Kenneth Palomino ,  Mahalingam Nandakumar

IPC: H01L21/324 ,  H01L49/02 ,  H01L27/07 ,  H01L21/225 ,  H01L21/268 ,  H01L27/06 ,  H01L21/265

Abstract: A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer thereon including a field dielectric in a portion of the semiconductor surface layer and a pair of matched devices in at least one of a CMOS area, BiCMOS area, bipolar transistor area, and a resistor area. Dopants are ion implanted into the at least one of the CMOS area, the BiCMOS area, the bipolar transistor area, and the resistor area. The substrate is annealed in a processing chamber of a rapid thermal processor (RTP). The annealing comprises an initial temperature stabilization step including first annealing at a lower temperature for a first time of at least 20 seconds, and then a second annealing comprising ramping from the lower temperature to a peak higher temperature that is at least 100° C. higher (>) than the lower temperature.

公开(公告)号：US09721847B2

公开(公告)日：2017-08-01

申请号：US14724185

申请日：2015-05-28

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Brian K. Kirkpatrick

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/324 ,  H01L21/3213 ,  H01L21/477 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/32131 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.

公开(公告)号：US09620423B2

公开(公告)日：2017-04-11

申请号：US14878553

申请日：2015-10-08

Applicant: Texas Instruments Incorporated

Inventor： Brian K. Kirkpatrick ,  Amitabh Jain

IPC: H01L29/76 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/092 ,  H01L29/161

CPC classification number: H01L27/092 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/823864 ,  H01L29/161 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/778 ,  H01L29/7833

Abstract: A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

公开(公告)号：US20150187653A1

公开(公告)日：2015-07-02

申请号：US14567507

申请日：2014-12-11

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Brian K. Kirkpatrick

IPC: H01L21/8238 ,  H01L21/28

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/32131 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.

公开(公告)号：US20140080301A1

公开(公告)日：2014-03-20

申请号：US14089958

申请日：2013-11-26

Applicant: Texas Instruments Incorporated

Inventor： Brian K. Kirkpatrick ,  Rajesh Tiwari

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L23/481 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor die includes circuit elements configured to provide a circuit function. A substrate including a bottomside and a topside is provided. At least one multi-layer structure is formed. The forming is done by depositing a coefficient of thermal expansion (CTE) graded layer comprising at least a dielectric portion on a first material having a first CTE to provide a first side facing said first material and a second side opposite the first side. The depositing includes flowing a first reactive component and at least a second reactive component. A gas flow ratio of the first reactive component relative to the second reactive component is automatically changed during a deposition time to provide a non-constant composition profile which has a graded CTE that increases from the first side to the second side. A metal layer comprising a second material having a second CTE is formed on the second side. The second CTE is higher than the first CTE.

Abstract translation: 制造半导体管芯的方法包括配置成提供电路功能的电路元件。 提供了包括底部和顶部的底物。 形成至少一个多层结构。 通过在包含第一CTE的第一材料上沉积包括至少介电部分的热膨胀系数（CTE）渐变层以提供面对所述第一材料的第一侧和与第一侧相对的第二侧来进行成型。 沉积包括流动第一反应组分和至少第二反应组分。 第一反应成分相对于第二反应成分的气体流量比在沉积时间期间自动变化，以提供具有从第一侧增加到第二侧的渐变CTE的非恒定组成分布。 包括具有第二CTE的第二材料的金属层形成在第二侧上。 第二个CTE高于第一个CTE。