公开(公告)号：US11848244B2

公开(公告)日：2023-12-19

申请号：US17491394

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L23/528 ,  H01L24/08 ,  H01L24/96 ,  H01L2224/08245 ,  H01L2224/08501

Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.

公开(公告)号：US20220208660A1

公开(公告)日：2022-06-30

申请号：US17139987

申请日：2020-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Ayumu Kuroda ,  Kengo Aoya

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: An electronic package includes an electronic component including terminals, a plurality of surface contacts, at least some of the surface contacts being electrically coupled to the terminals within the electronic package, a mold compound covering the electronic component and partially covering the surface contacts with a bottom surface exposed from the mold compound, and a plurality of wires extending from exposed surfaces of the surface contacts, each of the wires providing a solderable surface for mounting the electronic package at a standoff on an external board.

公开(公告)号：US11183460B2

公开(公告)日：2021-11-23

申请号：US16132906

申请日：2018-09-17

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/538 ,  H01L23/373 ,  H01L21/56 ,  H01L23/498

Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

公开(公告)号：US20150147845A1

公开(公告)日：2015-05-28

申请号：US14552548

申请日：2014-11-25

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mark Allen Gerber ,  Mutsumi Masumoto ,  Masamitsu Matsuura ,  Kengo Aoya ,  Takeshi Onogami

IPC: H01L25/00 ,  H01L21/304 ,  H01L21/683 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L21/561 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.

Abstract translation: 本发明的实施例提供了一种用于形成双面嵌入式模具系统的方法。 该方法从起始材料开始，包括顶表面和底表面，多个通孔，多个电镀金属柱，冲压垫和加强件。 将表面平坦化以暴露所包含的金属，其不是从管芯附着垫DAP区域选择性地蚀刻以形成空腔。 通过使用光刻胶图案和电镀创建一个加强筋。 涂抹胶带。 附上一个模具 层压和研磨。 去除胶带。 形式重新分配层RDL和焊接掩模。 安装表面贴装器件。

公开(公告)号：US08815648B1

公开(公告)日：2014-08-26

申请号：US13854400

申请日：2013-04-01

Applicant: Texas Instruments Incorporated

Inventor： Kengo Aoya ,  Shohta Ujiie ,  Kazunori Hayata

IPC: H01L29/66 ,  H01L23/00

CPC classification number: H01L24/85 ,  H01L21/4867 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48739 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/85065 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of assembling semiconductor devices includes applying a metal paste including a plurality of metal particles having an average size less than 50 nanometers and a binder material onto a metal terminal of a package substrate. The metal paste is processed including a heat up step in a reducing gas atmosphere and then a vacuum sintering step at a temperature of at least 200° C. for forming a sintered metal coating. A semiconductor die is attached onto a die attach area of the package substrate. A bond wire is then connected between a bond pad on the semiconductor die and the sintered metal coating on the metal terminal.

Abstract translation: 一种组装半导体器件的方法包括将包含平均尺寸小于50纳米的多个金属颗粒和粘合剂材料的金属膏施加到封装衬底的金属端子上。 处理包括加热步骤在还原气体气氛中的金属糊料，然后在至少200℃的温度下进行真空烧结步骤以形成烧结金属涂层。 将半导体管芯附着到封装衬底的管芯附着区域上。 然后将接合线连接在半导体管芯上的接合焊盘和金属端子上的烧结金属涂层之间。

公开(公告)号：US20250087591A1

公开(公告)日：2025-03-13

申请号：US18960733

申请日：2024-11-26

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matasuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar ,  Hideaki Matsunaga

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

公开(公告)号：US12125799B2

公开(公告)日：2024-10-22

申请号：US17517608

申请日：2021-11-02

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3735 ,  H01L23/49861

Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

公开(公告)号：US12046542B2

公开(公告)日：2024-07-23

申请号：US17246056

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Makoto Yoshino ,  Kengo Aoya

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/49

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/4885 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49 ,  H01L23/49506 ,  H01L23/4952 ,  H01L23/49582

Abstract: In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.

公开(公告)号：US11942384B2

公开(公告)日：2024-03-26

申请号：US17515234

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Masamitsu Matsuura ,  Kengo Aoya ,  Hideaki Matsunaga ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/3107 ,  H01L23/4952 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16245 ,  H01L2224/48245

Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.

公开(公告)号：US11923320B2

公开(公告)日：2024-03-05

申请号：US17139417

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Tomoko Noguchi ,  Mutsumi Masumoto ,  Kengo Aoya ,  Masamitsu Matsuura

IPC: H01L21/78 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48245

Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.