公开(公告)号：US08324660B2

公开(公告)日：2012-12-04

申请号：US12845593

申请日：2010-07-28

申请人： Anthony J. Lochtefeld ,  Matthew T. Currie ,  Zhiyuan Cheng ,  James Fiorenza ,  Glyn Braithwaite ,  Thomas A. Langdo

发明人： Anthony J. Lochtefeld ,  Matthew T. Currie ,  Zhiyuan Cheng ,  James Fiorenza ,  Glyn Braithwaite ,  Thomas A. Langdo

IPC分类号： H01L21/02

CPC分类号： H01L21/02609 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78687 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/036 ,  H01L31/1808 ,  H01L33/20 ,  H01L33/30 ,  H01L33/34 ,  Y02E10/50

摘要： Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

摘要翻译： 具有有限区域的单片晶格失配的半导体异质结构的制造，其具有基本上耗尽穿透位错的上部，以及基于这种晶格失配的异质结构的半导体器件的制造。

公开(公告)号：US07638842B2

公开(公告)日：2009-12-29

申请号：US11220482

申请日：2005-09-07

申请人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Zhiyuan Cheng ,  Thomas A. Langdo

发明人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Zhiyuan Cheng ,  Thomas A. Langdo

IPC分类号： H01L23/62

CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/7842 ,  H01L29/78687 ,  H01L2924/0002 ,  H01L2924/00

摘要： Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.

摘要翻译： 通过将形成在其上的替代活性区域材料的图案化衬底接合到刚性电介质平台上，然后与下面的衬底一起去除高缺陷界面区域以产生置于绝缘体上的替代有源区域区域来制造单片晶格失配的半导体异质结构 并且基本上耗尽了错配和穿线位错。

公开(公告)号：US20100206216A1

公开(公告)日：2010-08-19

申请号：US12711560

申请日：2010-02-24

申请人： Eugene A. Fitzgerald ,  Richard Westhoff ,  Matthew T. Currie ,  Christopher J. Vineis ,  Thomas A. Langdo

发明人： Eugene A. Fitzgerald ,  Richard Westhoff ,  Matthew T. Currie ,  Christopher J. Vineis ,  Thomas A. Langdo

IPC分类号： C30B25/00

CPC分类号： C30B29/52 ,  C23C16/029 ,  C23C16/22 ,  C23C16/4401 ,  C30B25/02 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262

摘要： A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.

摘要翻译： 在半导体材料上沉积梯度Si 1-x Ge x层的过程中使颗粒产生最小化的方法包括在包括Si前体和Ge前体的气氛中提供衬底，其中Ge前体具有分解 温度大于锗烷，并沉积具有大于约0.15的最终Ge含量并且小于约0.3颗粒/ cm 2的颗粒密度的梯度Si 1-x Ge 2层在衬底上 。

公开(公告)号：US07566606B2

公开(公告)日：2009-07-28

申请号：US11544245

申请日：2006-10-06

申请人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Christopher W. Leitz ,  Eugene A. Fitzgerald

发明人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Christopher W. Leitz ,  Eugene A. Fitzgerald

IPC分类号： H01L21/00

CPC分类号： H01L29/66545 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66916 ,  H01L29/802 ,  Y10S438/938

摘要： A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.

摘要翻译： 半导体结构包括锗浓度为至少10原子％的应变诱导基底层。 半导体结构还包括在应变诱导基底层上的压缩应变层。 压缩应变层的锗浓度比应变诱导基底层的锗浓度大至少约30个百分点，并且具有小于其临界厚度的厚度。 半导体结构还包括在压缩应变层上的拉伸应变层。 拉伸应变层可以由厚度小于其临界厚度的硅形成。 一种用于制造半导体结构的方法包括：提供衬底，在衬底上提供压缩应变半导体，在衬底附近沉积拉伸应变半导体，直到拉伸应变半导体的第一区域的厚度大于第二区域的厚度 的拉伸应变半导体，在第一区域上形成n沟道器件，并在第二区域上形成p沟道器件。

公开(公告)号：US07138649B2

公开(公告)日：2006-11-21

申请号：US10164665

申请日：2002-06-07

申请人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Eugene A. Fitzgerald

发明人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Eugene A. Fitzgerald

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L27/0922

摘要： A semiconductor structure having a substrate with a surface layer including strained silicon. The surface layer has a first region with a first thickness less than a second thickness of a second region. A gate dielectric layer is disposed over a portion of at least the first surface layer region.

公开(公告)号：US07138310B2

公开(公告)日：2006-11-21

申请号：US10456926

申请日：2003-06-06

申请人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Christopher W. Leitz ,  Eugene A. Fitzgerald

发明人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Christopher W. Leitz ,  Eugene A. Fitzgerald

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66916 ,  H01L29/802 ,  Y10S438/938

摘要： A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.

摘要翻译： 半导体结构包括锗浓度为至少10原子％的应变诱导基底层。 半导体结构还包括在应变诱导基底层上的压缩应变层。 压缩应变层的锗浓度比应变诱导基底层的锗浓度大至少约30个百分点，并且具有小于其临界厚度的厚度。 半导体结构还包括在压缩应变层上的拉伸应变层。 拉伸应变层可以由厚度小于其临界厚度的硅形成。 一种用于制造半导体结构的方法包括：提供衬底，在衬底上提供压缩应变半导体，在衬底附近沉积拉伸应变半导体，直到拉伸应变半导体的第一区域的厚度大于第二区域的厚度 的拉伸应变半导体，在第一区域上形成n沟道器件，并在第二区域上形成p沟道器件。

公开(公告)号：US07674335B2

公开(公告)日：2010-03-09

申请号：US11371442

申请日：2006-03-09

申请人： Eugene A. Fitzgerald ,  Richard Westhoff ,  Matthew T. Currie ,  Christopher J. Vineis ,  Thomas A. Langdo

发明人： Eugene A. Fitzgerald ,  Richard Westhoff ,  Matthew T. Currie ,  Christopher J. Vineis ,  Thomas A. Langdo

IPC分类号： C30B21/02

CPC分类号： C30B29/52 ,  C23C16/029 ,  C23C16/22 ,  C23C16/4401 ,  C30B25/02 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262

摘要： A method for minimizing particle generation during deposition of a graded Si1−xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1−xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.

摘要翻译： 在半导体材料上沉积梯度Si1-xGex层期间最小化颗粒产生的方法包括在包括Si前体和Ge前体的气氛中提供衬底，其中Ge前体的分解温度大于锗烷，并沉积 分级的Si1-xGex层，其具有大于约0.15的最终Ge含量和小于约0.3颗粒/ cm 2的颗粒密度。

公开(公告)号：US20110177681A1

公开(公告)日：2011-07-21

申请号：US13074777

申请日：2011-03-29

申请人： Eugene A. Fitzgerald ,  Richard Westhoff ,  Matthew T. Currie ,  Christopher J. Vineis ,  Thomas A. Langdo

发明人： Eugene A. Fitzgerald ,  Richard Westhoff ,  Matthew T. Currie ,  Christopher J. Vineis ,  Thomas A. Langdo

IPC分类号： H01L21/20

CPC分类号： C30B29/52 ,  C23C16/029 ,  C23C16/22 ,  C23C16/4401 ,  C30B25/02 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262

摘要： A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.

摘要翻译： 在半导体材料上沉积梯度Si1-xGex层期间最小化颗粒产生的方法包括在包括Si前体和Ge前体的气氛中提供衬底，其中Ge前体的分解温度大于锗烷，并沉积 分级的Si1-xGex层，其具有大于约0.15的最终Ge含量和小于约0.3颗粒/ cm 2的颗粒密度。

公开(公告)号：US07041170B2

公开(公告)日：2006-05-09

申请号：US10392338

申请日：2003-03-19

申请人： Eugene A. Fitzgerald ,  Richard Westhoff ,  Matthew T. Currie ,  Christopher J. Vineis ,  Thomas A. Langdo

发明人： Eugene A. Fitzgerald ,  Richard Westhoff ,  Matthew T. Currie ,  Christopher J. Vineis ,  Thomas A. Langdo

IPC分类号： C30B29/05

CPC分类号： C30B29/52 ,  C23C16/029 ,  C23C16/22 ,  C23C16/4401 ,  C30B25/02 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262

摘要： A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.

摘要翻译： 在半导体材料上沉积梯度的Si 1-x N x N x层的最小化颗粒产生的方法包括在包括Si前体和Ge的气氛中提供衬底 前体，其中所述Ge前体具有大于锗烷的分解温度，以及沉积具有大于约0.15的最终Ge含量的分级的Si 1-x N x Ge x层;以及 衬底上的颗粒密度小于约0.3颗粒/ cm 2。

公开(公告)号：US08106380B2

公开(公告)日：2012-01-31

申请号：US12982101

申请日：2010-12-30

申请人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Richard Hammond ,  Eugene Fitzgerald

发明人： Matthew T. Currie ,  Anthony J. Lochtefeld ,  Richard Hammond ,  Eugene Fitzgerald

IPC分类号： H01L21/00

CPC分类号： H01L29/1054 ,  H01L29/105 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7842 ,  Y10S438/926

摘要： Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

摘要翻译： 包括具有无杂质区域的应变材料层的半导体结构和器件及其制造方法。 应变材料层的某些区域保持没有可以从半导体的相邻部分相互扩散的杂质。 当杂质存在于应变材料层的某些区域中时，器件性能下降。 通过采用具有所描述的或者根据所描述的步骤制造的特征的半导体结构和器件（例如，场效应晶体管或“FET”），器件操作被增强。