公开(公告)号：US06582856B1

公开(公告)日：2003-06-24

申请号：US09513872

申请日：2000-02-28

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

IPC: G03F900

CPC classification number: G03F1/29

Abstract: A new method of fabricating a rim phase shifting mask is achieved. An opaque layer is provided overlying a transparent substrate. A resist layer is deposited overlying the opaque layer. The resist layer is patterned. The opaque layer and the transparent substrate are etched. The resist layer masks this etching. The opaque layer is etched through during this etching. Notches are thereby etched into the transparent substrate at the edges of the opaque layer. These notches will cause a phase shift in incident light relative to incident light passing through regions in the transparent substrate adjacent to the notches. During this etching, an overetch is performed to remove any mask defects in the transparent substrate. Optionally, the notches may be etched into a phase shifting layer overlying the transparent substrate. An etch stopping layer may also be used in the phase shifting layer embodiment.

Abstract translation: 实现了制作边缘相移掩模的新方法。 在透明基底上方设置不透明层。 将抗蚀剂层沉积在不透明层上。 抗蚀剂层被图案化。 蚀刻不透明层和透明基板。 抗蚀剂层掩盖该蚀刻。 在该蚀刻期间蚀刻不透明层。 因此，在不透明层的边缘处，凹口被蚀刻到透明基板中。 这些凹口将引起入射光相对于穿过透明衬底中与凹口相邻的区域的入射光的相移。 在该蚀刻期间，执行过蚀刻以去除透明基板中的任何掩模缺陷。 可选地，凹口可被蚀刻到覆盖透明衬底的相移层中。 在相移层实施例中也可以使用蚀刻停止层。

公开(公告)号：US06492726B1

公开(公告)日：2002-12-10

申请号：US09667837

申请日：2000-09-22

Applicant: Shyue Fong Quek ,  Ying Keung Leung ,  Sang Yee Loong ,  Ting Cheong Ang

Inventor： Shyue Fong Quek ,  Ying Keung Leung ,  Sang Yee Loong ,  Ting Cheong Ang

IPC: H01L2348

CPC classification number: H01L23/36 ,  H01L23/055 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In accordance with the objectives of the invention a new package is provided that is provided with a cavity that is shaped such that more than one semiconductor device can in a vertical direction be mounted in the cavity of the package. The devices that are mounted inside the cavity of the package are separated by separate components of insulation, the overlying devices are electrically interconnected by horizontally positioned solder bumps and vertical interconnect plugs.

Abstract translation: 根据本发明的目的，提供了一种新的封装，其具有形成使得多于一个半导体器件可以在垂直方向上可以安装在封装的空腔中的空腔。 安装在封装腔内的器件由绝缘体的分开的部件隔开，上覆的器件通过水平定位的焊料凸块和垂直互连插头电互连。

公开(公告)号：US06406948B1

公开(公告)日：2002-06-18

申请号：US09615807

申请日：2000-07-13

Applicant: Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

Inventor： Song Jun ,  Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek

IPC: H01L2184

CPC classification number: H01L27/0251 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate and patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. The interlevel dielectric layer is covered with a mask that covers the first contact openings. Second contact openings are opened through the interlevel dielectric layer, shallow trench isolations, and the oxide layer to the N+ region and P+ region. The mask is removed. The first and second contact openings are filled with a conducting layer to complete formation of an ESD device.

Abstract translation: 描述了使用绝缘体上硅技术形成静电放电装置的方法。 在硅半导体衬底内形成N阱。 将P +区注入到N阱的一部分内，并且将N +区注入到不被N阱占据的半导体衬底的一部分内。 在半导体衬底上形成氧化物层并图案化以形成到半导体衬底的开口。 外延硅层生长在开口内并覆盖氧化物层。 在延伸到下面的氧化物层的外延硅层内形成浅沟槽隔离区。 在浅沟槽隔离区域之间的外延硅层中和栅极电极和相关的源极和漏极区域上形成栅电极。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 用覆盖第一接触开口的掩模覆盖层间电介质层。 第二接触开口通过层间介质层，浅沟槽隔离层和氧化物层开放到N +区域和P +区域。 去除面具。 第一和第二接触开口填充有导电层以完成ESD装置的形成。

公开(公告)号：US06376319B2

公开(公告)日：2002-04-23

申请号：US09972629

申请日：2001-10-09

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

Abstract: A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

Abstract translation: 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

公开(公告)号：US06319783B1

公开(公告)日：2001-11-20

申请号：US09443425

申请日：1999-11-19

Applicant: Ting Cheong Ang ,  Shyue Pong Quek ,  Jun Song ,  Xing Yu

Inventor： Ting Cheong Ang ,  Shyue Pong Quek ,  Jun Song ,  Xing Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

Abstract: A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

Abstract translation: 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

公开(公告)号：US09029978B2

公开(公告)日：2015-05-12

申请号：US13456079

申请日：2012-04-25

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L29/00 ,  H01L21/762

CPC classification number: H01L21/76224

Abstract: A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide.

Abstract translation: 半导体结构包括具有衬底区域的半导体衬底和延伸到半导体衬底的表面区域中的沟槽。 沟槽包括侧壁，底部和深度。 半导体结构还包括覆盖沟槽的底部和侧壁的沟槽衬垫。 半导体结构还包括至少填充沟槽的深度的浅沟槽隔离结构。 浅沟槽隔离结构由氮化硅和高密度等离子体氧化物的交替层形成。

公开(公告)号：US08309456B2

公开(公告)日：2012-11-13

申请号：US11249141

申请日：2005-10-11

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L29/04

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76871

Abstract: A method for making an electrode in a semiconductor device. The method includes forming a trench in a first layer. The first layer is associated with a top surface, and the trench is associated with a bottom surface and a side surface. Additionally, the method includes depositing a diffusion barrier layer on at least the bottom surface, the side surface, and a part of the top surface, removing the diffusion barrier layer from at least a part of the bottom surface, depositing a seed layer on at least the part of the bottom surface and the diffusion barrier layer, and depositing an electrode layer on the seed layer.

Abstract translation: 一种在半导体器件中制造电极的方法。 该方法包括在第一层中形成沟槽。 第一层与顶表面相关联，并且沟槽与底表面和侧表面相关联。 此外，该方法包括在至少底表面，侧表面和顶表面的一部分上沉积扩散阻挡层，从底表面的至少一部分去除扩散阻挡层，将种子层沉积在 至少部分底表面和扩散阻挡层，以及在种子层上沉积电极层。

公开(公告)号：US07989309B2

公开(公告)日：2011-08-02

申请号：US11549116

申请日：2006-10-13

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/76

CPC classification number: H01L21/76232

Abstract: A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes etching the substrate region to increase the depth of at least a portion of the trench to a second depth.

Abstract translation: 提供了形成浅沟槽隔离区域的分级沟槽的方法。 该方法包括提供具有衬底区域的半导体衬底。 该方法还包括形成覆盖衬底区域的衬垫氧化物层。 另外，该方法包括形成覆盖衬垫氧化物层的蚀刻停止层。 该方法还包括图案化蚀刻停止层和衬垫氧化物层以暴露衬底区域的一部分。 此外，该方法包括在衬底区域的暴露部分内形成沟槽，沟槽具有侧壁和底部以及第一深度。 该方法另外包括形成覆盖沟槽侧壁，沟槽底部和与沟槽相邻的台面区域的介电层。 该方法还包括蚀刻衬底区域以将沟槽的至少一部分的深度增加到第二深度。

公开(公告)号：US06803314B2

公开(公告)日：2004-10-12

申请号：US09845480

申请日：2001-04-30

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Yee Chong Wong ,  Sang Yee Long

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Yee Chong Wong ,  Sang Yee Long

IPC: H01L21302

CPC classification number: H01L21/76835 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02131 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/022 ,  H01L21/3121 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76813

Abstract: A double layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first organic dielectric layer is deposited overlying the insulating layer. A second inorganic dielectric layer is deposited overlying the first dielectric layer. In a first method, a via pattern is etched into the second dielectric layer. The via pattern is etched into the first dielectric layer using the patterned second dielectric layer as a mask. Thereafter, a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings. In a second method, a trench pattern is etched into the second dielectric layer. Thereafter, a via pattern is etched through the second inorganic dielectric layer and the first organic dielectric layer to complete dual damascene openings. In a third method, a via pattern is etched into the second dielectric layer. Then, simultaneously, the via pattern is etched into the first dielectric layer and a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings in the fabrication of an integrated circuit device.

Abstract translation: 描述了双层低介电常数材料双镶嵌金属化工艺。 金属线被覆盖在半导体衬底上的绝缘层所覆盖。 沉积在绝缘层上的第一有机电介质层。 第二无机介电层沉积在第一介电层上。 在第一种方法中，通孔图案被蚀刻到第二介电层中。 使用图案化的第二介电层作为掩模将通孔图案蚀刻到第一介电层中。 此后，将沟槽图案蚀刻到第二无机介电层中以完成双镶嵌开口。 在第二种方法中，沟槽图案被蚀刻到第二介电层中。 此后，通过第二无机介电层和第一有机介电层蚀刻通孔图案以完成双镶嵌开口。 在第三种方法中，通孔图案被蚀刻到第二介电层中。 然后，同时，通孔图案被蚀刻到第一介电层中，并且沟槽图案被蚀刻到第二无机介电层中，以在集成电路器件的制造中完成双镶嵌开口。

公开(公告)号：US06764914B2

公开(公告)日：2004-07-20

申请号：US10290130

申请日：2002-11-07

Applicant: Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

Inventor： Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC: H01L2120

CPC classification number: H01L28/40 ,  H01L21/31683

Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

Abstract translation: 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。