公开(公告)号：US20080073682A1

公开(公告)日：2008-03-27

申请号：US11898949

申请日：2007-09-18

申请人： Yoshinori Kumura ,  Tohru Ozaki ,  Iwao Kunishima

发明人： Yoshinori Kumura ,  Tohru Ozaki ,  Iwao Kunishima

IPC分类号： H01L29/94 ,  H01L21/00

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57

摘要： According to an aspect of the present invention, there is provided a non-volatile semiconductor memory device, including a ferroelectric capacitor being stacked a first electrode, a ferroelectric film and a second electrode in order, a first protective film with hydrogen barrier performance, the first protective film being formed under the first electrode and on a side-wall of the ferroelectric capacitor, the first protective film being widened from the second electrode towards the first electrode, a second protective film with hydrogen barrier performance, the second protective film being formed over the second electrode and on the first protective film formed on the side-wall of the ferroelectric capacitor, the second protective film being widened from the first electrode towards the second electrode, a cell transistor, a source of the cell transistor being connected to the first electrode, a drain of the cell transistor being connected to a bit line and a gate being connected to a word line.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括堆叠第一电极，铁电体膜和第二电极的铁电电容器，具有氢阻挡性能的第一保护膜， 第一保护膜形成在第一电极下方和铁电电容器的侧壁上，第一保护膜从第二电极朝向第一电极加宽，具有氢阻挡性能的第二保护膜，形成第二保护膜 在第二电极上以及形成在铁电电容器的侧壁上的第一保护膜上，第二保护膜从第一电极朝向第二电极加宽，单元晶体管，单元晶体管的源极连接到 第一电极，单元晶体管的漏极连接到位线，栅极连接到aw ord行。

公开(公告)号：US20070072310A1

公开(公告)日：2007-03-29

申请号：US11364224

申请日：2006-03-01

申请人： Yoshinori Kumura ,  Tohru Ozaki ,  Susumu Shuto

发明人： Yoshinori Kumura ,  Tohru Ozaki ,  Susumu Shuto

IPC分类号： H01L21/00 ,  H01L21/8242 ,  H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11507 ,  H01L21/76834 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11509 ,  H01L28/57 ,  H01L28/65

摘要： A semiconductor device comprising a semiconductor substrate and memory cells. Each memory cell comprises a switching transistor and a ferroelectric capacitor, both formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film held between the lower and upper electrodes. A first wire formed from a deposited wire-material film is connected to the upper electrode of the ferroelectric capacitor. A second wire formed by damascene process is provided on the first wire.

摘要翻译： 一种半导体器件，包括半导体衬底和存储单元。 每个存储单元包括形成在基板上的开关晶体管和铁电电容器。 铁电电容器包括保持在下电极和上电极之间的下电极，上电极和铁电膜。 由沉积的线材膜形成的第一线连接到铁电电容器的上电极。 通过镶嵌工艺形成的第二丝线设置在第一线上。

公开(公告)号：US06611015B2

公开(公告)日：2003-08-26

申请号：US09956001

申请日：2001-09-20

申请人： Tohru Ozaki ,  Iwao Kunishima ,  Toyota Morimoto ,  Hiroyuki Kanaya

发明人： Tohru Ozaki ,  Iwao Kunishima ,  Toyota Morimoto ,  Hiroyuki Kanaya

IPC分类号： H01L27108

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.

摘要翻译： 一种半导体存储器件，包括具有形成在半导体衬底上的多个存储晶体管的存储单元块。 存储晶体管包括第一和第二杂质扩散区域以及在它们之间形成的栅极。 多个存储单元也包括在存储单元块中，并且具有连接到第一杂质扩散区的下电极，形成在下电极上的铁电膜和形成在铁电体膜上的第一上电极并连接到第二杂质扩散区 地区。 还包括形成在半导体衬底上并连接到存储单元块的一端的块选择晶体管。 第二上电极也形成为与块选择晶体管相邻并且与存储单元的第一上电极断开连接。

公开(公告)号：US5747844A

公开(公告)日：1998-05-05

申请号：US736279

申请日：1996-10-24

申请人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

发明人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

IPC分类号： H01L21/822 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10882 ,  Y10S257/907

摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

公开(公告)号：US5629539A

公开(公告)日：1997-05-13

申请号：US400887

申请日：1995-03-08

申请人： Masami Aoki ,  Tohru Ozaki ,  Takashi Yamada ,  Hitomi Kawaguchiya

发明人： Masami Aoki ,  Tohru Ozaki ,  Takashi Yamada ,  Hitomi Kawaguchiya

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L29/94

摘要： A semiconductor memory device comprises a semiconductor substrate, a plurality of memory cells including a plurality of MOS transistors, each having a source, a drain and a gate, and a plurality of capacitors formed on the semiconductor substrate in a matrix manner, an interlayer insulating film formed on the memory cells and having a plurality of openings selectively formed, a plurality of plug electrodes formed in the openings of the interlayer insulating film, a plurality of bit lines, each bit line being connected to one of the source and the drain of each of the MOS transistors through a corresponding one of the plug electrodes, and a plurality word lines, each word line being the gate of each of the MOS transistors. The capacitors each comprise a storage node electrode having a cylindrical portion layered on another one of the source and the drain of each of the MOS transistors, a capacitor dielectric film formed on the storage node electrode, and a plate electrode formed to be opposed to at least the storage node electrode interposing the capacitor dielectric film therebetween. The bit lines are formed on the interlayer insulating film and connected to the upper surface of the plug electrode. The plug electrode has a pad electrode comprised of a lower side conductive member formed with a same layer as the storage node electrode and a cylindrical side wall conductive member, and an upper side conductive member formed on the pad electrode.

摘要翻译： 半导体存储器件包括半导体衬底，包括多个MOS晶体管的多个存储单元，每个MOS晶体管具有源极，漏极和栅极以及以矩阵方式形成在半导体衬底上的多个电容器，层间绝缘 形成在存储单元上并具有选择性地形成的多个开口的多个插塞电极，形成在层间绝缘膜的开口中的多个插塞电极，多个位线，每个位线连接到源极和漏极之一 每个MOS晶体管通过相应的一个插头电极和多个字线，每个字线是每个MOS晶体管的栅极。 电容器各自包括存储节点电极，其具有层叠在每个MOS晶体管的源极和漏极的另一个上的圆柱形部分，形成在存储节点电极上的电容器电介质膜和形成为与 存储节点电极至少插入电容器电介质膜之间。 位线形成在层间绝缘膜上并连接到插塞电极的上表面。 插头电极具有由形成有与蓄电节点电极相同层的下侧导电部件和圆筒状侧壁导电部件构成的焊盘电极，以及形成在焊盘电极上的上侧导电部件。

公开(公告)号：US5362521A

公开(公告)日：1994-11-08

申请号：US036407

申请日：1993-03-24

申请人： Tohru Ozaki ,  Akira Kasari ,  Shigeru Nakamura

发明人： Tohru Ozaki ,  Akira Kasari ,  Shigeru Nakamura

IPC分类号： B05D5/06 ,  B05D7/00 ,  C08L61/28 ,  C08L83/04 ,  C09D5/00 ,  C09D5/38 ,  C09D201/06 ,  B05D1/36

CPC分类号： B05D7/532 ,  B05D5/068 ,  B05D7/577 ,  C09D201/06 ,  C09D5/002 ,  C09D5/38 ,  B05D2601/04 ,  C08L61/28 ,  C08L83/04

摘要： The invention provides a method of forming a coating film by forming in sequence a pigmented base coat and a clear top coat on a substrate followed by finishing by the two-coat one-bake technique, the method being characterized by using, as a coating composition for pigmented base coat formation, a composition comprising, as essential components thereof,(1) an OH-containing resin,(2) an amino resin,(3) a polyorganosiloxane which has, on an average, at least two groups, per molecule, each selected from the class consisting of a silanol group and an alkoxysilane group and has a number average molecular weight of at least 1,000,(4) a metal chelate compound(5) a flaky metal powder and/or a mica powder, and(6) an organic solvent,and using, as a coating composition for clear top coat formation, a composition comprising, as essential components thereof,(1) an OH- and epoxy-containing base resin which further contains at least one group selected from the group consisting of a silanol group and a hydrolyzable group bound directly to a silicon atom,(2) a curing catalyst, and(3) an organic solvent.

摘要翻译： 本发明提供了一种形成涂膜的方法，该方法通过在基材上依次形成着色底涂层和透明面漆，然后通过双涂层单烘烤技术进行精加工，该方法的特征在于使用作为涂料组合物 对于着色底涂层形成，包含作为其主要组分的组合物，（1）含OH树脂，（2）氨基树脂，（3）每分子平均具有至少两个基团的聚有机硅氧烷 各自选自由硅烷醇基和烷氧基硅烷基组成的类别，数均分子量为1,000以上，（4）金属螯合物（5）为片状金属粉末和/或云母粉末，（ 6）有机溶剂，并且使用作为透明外涂层形成用涂料组合物的组合物，其包含作为其主要组分的组合物，（1）含OH-和环氧基的基础树脂，其还含有至少一种选自 由硅烷醇组成的组 （2）固化催化剂，和（3）有机溶剂。

公开(公告)号：US5087969A

公开(公告)日：1992-02-11

申请号：US554365

申请日：1990-07-19

申请人： Hiroshi Kamada ,  Tohru Ozaki

发明人： Hiroshi Kamada ,  Tohru Ozaki

IPC分类号： G05D1/02

CPC分类号： G05D1/0246 ,  G05D1/0221 ,  G05D1/0234 ,  G05D2201/0213 ,  Y10S706/90

摘要： A system for controlling an unmanned vehicle by detection of a guide line based on a picture image picked up by a camera on the vehicle, including a parameter (.rho., .theta.) deriving unit for deriving parameters (.rho., .theta.) of point extracted from a picture image picked up by a camera, and a maximum density parameter detection unit for integrating the densities of parameters derived by the parameter deriving unit and determining the maximum density parameter from the integrated densities of the parameters. The maximum density parameter is determined from the parameter derived by the parameter deriving unit, for the parameter area having at the center thereof the parameter estimated from the maximum density parameter, and the detected maximum density parameter is decided as the parameter of said guide line. The determination of steered amount by a fuzzy inference can be used.

公开(公告)号：US4791678A

公开(公告)日：1988-12-13

申请号：US161274

申请日：1988-02-22

申请人： Hiromichi Iwase ,  Shigeru Sasaki ,  Toshiyuki Gotoh ,  Takashi Toriu ,  Tohru Ozaki

发明人： Hiromichi Iwase ,  Shigeru Sasaki ,  Toshiyuki Gotoh ,  Takashi Toriu ,  Tohru Ozaki

IPC分类号： G06T5/00 ,  G06K9/36 ,  G06K9/80 ,  G06T5/20 ,  G06T7/00 ,  G06K9/40

CPC分类号： G06T5/20

摘要： An image processing system mainly used in an image verification system for detecting and correcting distortion of an input image includes the following devices; an image memory for storing a digitized image before, during, and after correction, a working memory for temporarily storing intermediate data of the image on correction, density level extension devices for extending the density level or gradation of the image by repeatedly reading out the contents of the image memory and the working memory by using a matrix window containing picture elements of the image, a density slope detection device for detecting the extended density level and calculating a density slope or gradient by using the matrix window, and a correction device for correcting density distribution and line width of the image based on the extended density level and the calculated density slope.

摘要翻译： 主要用于检测和校正输入图像失真的图像验证系统中的图像处理系统包括以下装置; 用于在校正之前，之中和之后存储数字化图像的图像存储器，用于临时存储修正图像的中间数据的工作存储器，用于通过重复读出内容来扩展图像的浓度级或灰度级的浓度级扩展装置 通过使用包含图像的图像的矩阵窗口的图像存储器和工作存储器，密度斜率检测装置，用于通过使用矩阵窗口来检测扩展密度级别并计算密度斜率或梯度;以及校正装置， 基于扩展密度水平和计算密度斜率的图像的密度分布和线宽。

公开(公告)号：US08476693B2

公开(公告)日：2013-07-02

申请号：US13050297

申请日：2011-03-17

申请人： Takayuki Toba ,  Tohru Ozaki

发明人： Takayuki Toba ,  Tohru Ozaki

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/11534 ,  H01L29/66825

摘要： In one embodiment, a nonvolatile semiconductor memory includes a memory cell array, a first silicon nitride film and a second silicon nitride film. The memory cell array includes NAND cell units. Each of the NAND cell units has memory cell transistors, a source-side select gate transistor and a drain-side select gate transistor. The source-side select gate transistors is disposed in such a manner as to face each other and the drain-side select gate transistors is disposed in such a manner as to face each other. The first silicon nitride film is present in a region between the source-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate. The second silicon nitride film is formed in a region between the drain-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate.

摘要翻译： 在一个实施例中，非易失性半导体存储器包括存储单元阵列，第一氮化硅膜和第二氮化硅膜。 存储单元阵列包括NAND单元单元。 每个NAND单元单元具有存储单元晶体管，源极选择栅极晶体管和漏极侧选择栅极晶体管。 源极侧选择栅极晶体管以彼此面对的方式设置，并且漏极侧选择栅极晶体管以彼此面对的方式设置。 第一氮化硅膜存在于源极选择栅晶体管之间的区域中，并且设置在从半导体衬底的上表面最低的位置。 第二氮化硅膜形成在漏极侧选择栅晶体管之间的区域中，并且设置在从半导体衬底的上表面最低的位置。

公开(公告)号：US20100072525A1

公开(公告)日：2010-03-25

申请号：US12553923

申请日：2009-09-03

申请人： Yoshiro Shimojo ,  Tohru Ozaki ,  Yoshinori Kumura

发明人： Yoshiro Shimojo ,  Tohru Ozaki ,  Yoshinori Kumura

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L27/11512 ,  H01L27/11507 ,  H01L28/55

摘要： According to a method for manufacturing a semiconductor memory device of the present invention, a capacitor lower electrode film is left on the wiring layer located above a dummy transistor. In this manner, when processing of the capacitors is performed by removing a capacitor upper electrode film and a ferroelectric film, removal of the wiring layer can be prevented, and the connection between the diffusion layer of a select transistor and a bit line can be secured.

摘要翻译： 根据本发明的半导体存储器件的制造方法，在位于虚拟晶体管上方的布线层上留下电容器下电极膜。 以这种方式，当通过去除电容器上电极膜和铁电体膜来执行电容器的处理时，可以防止布线层的去除，并且可以确保选择晶体管的扩散层和位线之间的连接 。