公开(公告)号：US20220246626A1

公开(公告)日：2022-08-04

申请号：US17719625

申请日：2022-04-13

Applicant: Tokyo Electron Limited

Inventor： Soo Doo Chae ,  Sang Cheol Han ,  Youngwoo Park

IPC: H01L27/11524 ,  H01L27/11582

Abstract: Embodiments provide raised pad formations for step contacts in three-dimensional structures formed on microelectronic workpieces. Steps are formed in a multilayer stack that is used for the three-dimensional structure. The multilayer stack includes alternating non-conductive and conductive layers. For one embodiment, alternating oxide and polysilicon layers are used. The steps expose contact regions on different conductive layers. Material layers are formed on the contact regions to form raised pads. The material layers preferably have a high selectivity with respect to the non-conductive material for etch processes. A protective layer is formed over the steps and the raised pads, and contact holes are formed through the protective layer to the raised pads. Contacts are then formed within the contact holes. The raised pads inhibit punch-through of the non-conductive layers during the forming of the contact holes thereby improving performance of resulting devices formed in the microelectronic workpieces.

公开(公告)号：US10541174B2

公开(公告)日：2020-01-21

申请号：US15875442

申请日：2018-01-19

Applicant: Tokyo Electron Limited

Inventor： Soo Doo Chae ,  Jeffrey Smith ,  Gerrit J. Leusink ,  Robert D. Clark ,  Kai-Hung Yu

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/285

Abstract: A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

公开(公告)号：US10453749B2

公开(公告)日：2019-10-22

申请号：US15895736

申请日：2018-02-13

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Sangcheol Han ,  Soo Doo Chae

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3105 ,  H01L23/522 ,  H01L23/532

Abstract: A substrate processing method for forming a self-aligned contact using selective SiO2 deposition is described in various embodiments. The method includes providing a planarized substrate containing a dielectric layer surface and a metal-containing surface, coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO2 layer on the metal-containing catalyst layer on the dielectric layer surface. According to one embodiment, the method further includes depositing an etch stop layer on the SiO2 layer and on the metal-containing surfaces, depositing an interlayer dielectric layer on the planarized substrate, etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface, and filling the recessed feature with a metal.

公开(公告)号：US20190259650A1

公开(公告)日：2019-08-22

申请号：US16277744

申请日：2019-02-15

Applicant: Tokyo Electron Limited

Inventor： Sang Cheol Han ,  Soo Doo Chae ,  Kai-Hung Yu

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/02 ,  H01L23/532 ,  C23C16/06 ,  C23C16/56

Abstract: Methods are described for protecting cobalt (Co) metal plugs used for making electrical connections within a semiconductor device. In one example, method includes providing a substrate containing a Co metal plug in a dielectric layer, and selectively forming a ruthenium (Ru) metal cap layer on the Co metal plug. In another example, the method includes providing a substrate containing a Co metal plug in a first dielectric layer, selectively forming a Ru metal cap layer on the Co metal plug, depositing a second dielectric layer on the Ru metal cap layer and on the first dielectric layer, etching a recessed feature in the second dielectric layer to expose the Ru metal cap layer, and performing a cleaning process that removes polymer etch residue from the Ru metal cap layer in the recessed feature.

公开(公告)号：US20190187556A1

公开(公告)日：2019-06-20

申请号：US16221030

申请日：2018-12-14

Applicant: Tokyo Electron Limited

Inventor： Wanjae Park ,  Lior Huli ,  Soo Doo Chae

IPC: G03F7/00 ,  G03F7/20 ,  H01L21/027

CPC classification number: G03F7/0002 ,  G03F7/2022 ,  G03F7/70033 ,  H01L21/0276

Abstract: Embodiments of methods for patterning using enhancement of surface adhesion are presented. In an embodiment, a method for patterning using enhancement of surface adhesion may include providing an input substrate with an anti-reflective coating layer and an underlying layer. Such a method may also include performing a surface adhesion modification process on the substrate, the surface adhesion modification process utilizing a plasma treatment configured to increase an adhesion property of an anti-reflective coating layer without affecting downstream processes. In an embodiment, the method may also include performing a photoresist coating process, a mask exposure process, and a developing process to generate a target patterned structure in a photoresist layer on the substrate. In such embodiments, the method may include controlling operating parameters of the surface adhesion modification process to achieve target profiles of the patterned structure and substrate throughput objectives.

公开(公告)号：US20180350665A1

公开(公告)日：2018-12-06

申请号：US16001695

申请日：2018-06-06

Applicant: Tokyo Electron Limited

Inventor： Soo Doo Chae ,  Kaoru Maekawa ,  Jeffrey Smith ,  Nicholas Joy ,  Gerrit J. Leusink ,  Kai-Hung Yu

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: A substrate processing method is provided for metal filling of recessed features in a substrate. According to one embodiment, the method includes providing a substrate containing horizontally spaced nested and isolated recessed features, filling the nested and isolated recessed features with a blocking material, and performing in any order: a) sequentially first, removing the blocking material from the nested recessed features, and second, filling the nested recessed features with a first metal, and b) sequentially first, removing the blocking material from the isolated recessed features, and second, filling the isolated recessed features with a second metal that is different from the first metal. According to one embodiment, the first metal may include Ru metal and the second metal may include Cu metal. According to one embodiment, a microelectronic device containing metal filled recessed features is provided.

公开(公告)号：US11990425B2

公开(公告)日：2024-05-21

申请号：US17405265

申请日：2021-08-18

Applicant: Tokyo Electron Limited

Inventor： Hojin Kim ,  Stephen Mancini ,  Soo Doo Chae

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/31144 ,  H01L21/76224 ,  H01L22/12

Abstract: This disclosure describes a method for fabricating a plurality of semiconductor devices in a semiconductor wafer includes: bowing a semiconductor wafer including a substrate by covering the substrate with a strained layer; forming trenches at locations in scribe lines of the semiconductor wafer, the scribe lines identifying areas between adjacent dies on the semiconductor wafer; and reducing the bowing of the semiconductor wafer by filling the trenches with a stress-compensation material.

公开(公告)号：US20240147719A1

公开(公告)日：2024-05-02

申请号：US17978674

申请日：2022-11-01

Applicant: Tokyo Electron Limited

Inventor： Soo Doo Chae ,  Lior Huli ,  Steven Gueci ,  Hojin Kim ,  Henan Zhang ,  Na Young Bae

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: In certain embodiments, a method includes forming, on a substrate by spin-on deposition, a layer stack of alternating layers of first and second carbon-containing materials. The layers of the first carbon-containing material include an agent-generating ingredient for generating a solubility-changing agent in response to an activation trigger. The method includes executing the activation trigger in response to which the solubility-changing agent is generated from the agent-generating ingredient in the layers of the first carbon-containing material and modifies the layers of the first carbon-containing material to be soluble in a developer. The method includes etching first openings through the layer stack, filling the first openings with a third material, etching second openings through the layer stack, removing the layers of the first carbon-containing material from the layer stack by exposing those to the developer, and replacing the layers of the first carbon-containing material with a fourth material.

公开(公告)号：US20240145312A1

公开(公告)日：2024-05-02

申请号：US17975349

申请日：2022-10-27

Applicant: Tokyo Electron Limited

Inventor： Soo Doo Chae ,  Matthew Baron ,  Hojin Kim ,  Sunghil Lee

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/30625 ,  H01L21/76224

Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming, on a first side of a substrate, a first stack and a second stack. The method includes etching, from the first side, a portion of the substrate interposed between the first and second stacks to form a recess. The method includes filling the recess with a dielectric material to form an isolation structure. The method includes forming, on the first side, one or more first interconnect structures over the first and second stacks. The method includes removing, from a second side of the substrate opposite to the first side, a remaining portion of the substrate. The method includes forming a via structure extending through at least the isolation structure. The method includes forming, on the second side, one or more second interconnect structures.

公开(公告)号：US20230255014A1

公开(公告)日：2023-08-10

申请号：US17668838

申请日：2022-02-10

Applicant: Tokyo Electron Limited

Inventor： Sang Cheol Han ,  Soo Doo Chae ,  Sunghil Lee

IPC: H01L27/108 ,  G11C11/402

CPC classification number: H01L27/10864 ,  H01L27/10829 ,  G11C11/4023

Abstract: Technologies for fabricating a vertical dynamic random access memory (DRAM) structure include forming a DRAM cell hole through a word line layer and an associated substrate such that a first section of the DRAM cell hole extends through the word line layer and a second section of the DRAM cell hole extends through the substrate in vertical alignment with the first section. A pillar capacitor structure is initially formed using the second section of the DRAM cell hole, followed by the formation of a transistor using the first section of the DRAM cell hole as a channel for the transistor. Due to the use of a common DRAM cell hole, the pillar capacitor structure and the channel are in vertical alignment. The substrate is subsequently flipped and removed from the pillar capacitor structure, which is further processed to form a pillar capacitor. In some embodiments, the channel may be formed from a deposition of indium gallium zinc oxide (IGZO).