公开(公告)号：US20050258474A1

公开(公告)日：2005-11-24

申请号：US10484578

申请日：2002-07-22

Applicant: Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

Inventor： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

Abstract translation: 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US06542411B2

公开(公告)日：2003-04-01

申请号：US09970675

申请日：2001-10-05

Applicant: Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Yoshiki Kawajiri ,  Masamichi Fujito

Inventor： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Yoshiki Kawajiri ,  Masamichi Fujito

IPC: G11C1604

CPC classification number: G11C16/3472 ,  G11C16/30 ,  G11C16/3468 ,  G11C16/3481

Abstract: A nonvolatile memory includes a control register (CRG) for providing instructions as to basic operations such as writing, erasing, reading, etc., a boosted voltage attainment detecting circuit for detecting whether a voltage boosted by a booster circuit has reached a desired level, a circuit which counts the time required to apply each of write and erase voltages, and a circuit which detects the completion of the writing or erasing. Respective operations are automatically advanced by simple setting of the operation instructions to the control register. After the completion of the operations, an end flag (FLAG) provided within the control register is set to notify the completion of the writing or erasing.

Abstract translation: 非易失性存储器包括用于提供关于基本操作（诸如写入，擦除，读取等）的指令的控制寄存器（CRG），用于检测由升压电路升压的电压是否达到期望水平的升压电压达到检测电路， 计算施加写入和擦除电压中的每一个所需的时间的电路，以及检测写入或擦除完成的电路。 通过将操作指令简单设置到控制寄存器，可以自动提高各自的操作。 操作完成后，设置控制寄存器内提供的结束标志（FLAG），通知写入或擦除完成。

公开(公告)号：US06510086B2

公开(公告)日：2003-01-21

申请号：US09984918

申请日：2001-10-31

Applicant: Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

Inventor： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC: G11C1604

CPC classification number: G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

Abstract: Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to store the data in the nonvolatile memory, and the nonvolatile memory is capable of performing at least a program operation and an erase operation. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the erase operation. Also, the buffer memory is capable of receiving a unit of data, in the program operation, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Abstract translation: 公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。 控制装置能够接收外部数据并将数据存储在非易失性存储器中，并且非易失性存储器能够执行至少一个编程操作和擦除操作。 此外，当非易失性存储器在擦除操作中操作时，控制装置能够接收外部数据。 此外，缓冲存储器能够在程序操作中接收与程序运行一次要存储的数据的数据长度相等的数据单元，数据长度大于1字节。

公开(公告)号：US06459619B1

公开(公告)日：2002-10-01

申请号：US09986081

申请日：2001-11-07

Applicant: Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

Inventor： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

IPC: G11C1604

CPC classification number: G11C16/3409 ,  G11C8/08 ,  G11C16/12 ,  G11C16/3404

Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for-each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.

Abstract translation: 一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。 为每个字线提供字锁存电路，并且每个存储器单元的阈值电压被管理在所选存储器块中的每个字线。 每个字锁存电路由多个字线共享，以便减少所需的芯片面积。 为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

公开(公告)号：US6122196A

公开(公告)日：2000-09-19

申请号：US219435

申请日：1998-12-23

Applicant: Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

Inventor： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

IPC: G11C16/04 ,  G11C16/06 ,  G11C16/24 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/0416 ,  G11C16/24 ,  G11C16/30

Abstract: The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.

Abstract translation: 本发明提出了一种非易失性半导体存储器，包括多个主位线，连接到主位线的多个子位线以及多个存储单元阵列，每个存储单元阵列包括多个非易失性半导体存储器 细胞排列成阵列。 这些存储单元中的每一个具有源极端子，漏极端子和控制栅极，并且每个源极 - 漏极路径连接到子位线。 在主位线和连接到主位线的子位线之间设置第一晶体管的源极 - 漏极路径，并且第二晶体管的源极 - 漏极路径连接到子位线。

公开(公告)号：US5808944A

公开(公告)日：1998-09-15

申请号：US797654

申请日：1997-01-31

Applicant: Takayuki Yoshitake ,  Kazuyoshi Oshima ,  Kazuyuki Miyazawa ,  Toshihiro Tanaka ,  Yasuhiro Nakamura ,  Shigeru Tanaka ,  Atsushi Ohba

Inventor： Takayuki Yoshitake ,  Kazuyoshi Oshima ,  Kazuyuki Miyazawa ,  Toshihiro Tanaka ,  Yasuhiro Nakamura ,  Shigeru Tanaka ,  Atsushi Ohba

IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/80

Abstract: In a semiconductor storage device wherein data lines connected to a plurality of memory cells selected by a select operation of word lines are sequentially selected by using an address signal generated by an address counter to serially read data in individual unit of at least one word line: redundancy data lines disposed perpendicular to the word lines are provided; a column select circuit receiving a Y address signal selects one of the data lines or redundancy data lines; a redundancy memory circuit stores, in the order of the selection operation by the column select circuit, a defect address signal of a defect data line among the data lines and a redundancy address signal of a corresponding redundancy data line; an address comparator circuit compares one defect address signal read from the redundancy memory circuit with an address signal generated by the address counter; an address signal for the redundancy memory circuit is generated by performing a count operation in response to a coincidence signal generated by the address comparator circuit; and the address signal generated by the address counter is replaced by a redundancy address signal read in response to the coincidence signal from the redundancy memory circuit and used as the Y address signal. Accordingly, a redundancy circuit of simple configuration can be obtained because only a single address comparator circuit is used.

Abstract translation: 在半导体存储装置中，通过使用地址计数器生成的地址信号来顺序地选择连接到通过字线的选择操作选择的多个存储单元的数据线，以至少一个字线的单独串行读取数据： 提供与字线垂直设置的冗余数据线; 接收Y地址信号的列选择电路选择数据线或冗余数据线之一; 冗余存储电路按照列选择电路的选择操作的顺序存储数据线之间的缺陷数据线的缺陷地址信号和对应的冗余数据线的冗余地址信号; 地址比较器电路将从冗余存储器电路读取的一个缺陷地址信号与由地址计数器产生的地址信号进行比较; 通过响应于由地址比较器电路产生的一致信号执行计数操作来产生用于冗余存储器电路的地址信号; 并且由地址计数器产生的地址信号被响应于来自冗余存储器电路的符合信号读取并用作Y地址信号的冗余地址信号所替代。 因此，由于仅使用单个地址比较器电路，所以可以获得简单配置的冗余电路。

公开(公告)号：US5686379A

公开(公告)日：1997-11-11

申请号：US505286

申请日：1995-08-21

Applicant: Tatsuhiro Imanaka ,  Toshihiro Tanaka ,  Jun Kono ,  Hiroshi Nagumo ,  Hiroyuki Tamaura

Inventor： Tatsuhiro Imanaka ,  Toshihiro Tanaka ,  Jun Kono ,  Hiroshi Nagumo ,  Hiroyuki Tamaura

IPC: B01J21/10 ,  B01J23/00 ,  B01J37/03 ,  C07C41/03 ,  C07D295/00

CPC classification number: C07C41/03 ,  B01J21/10 ,  B01J23/002 ,  B01J37/03 ,  B01J2523/00

Abstract: An alkoxylation catalyst comprising metal oxides, having a basicity point expressed in pKa value from 9 to 25 and an acidity point expressed in the amount of ammonia gas adsorbed from 50 to 500 .mu.mol/g, and a process for preparing an alkoxylate with the use of this catalyst. According to the present invention, an alkoxylate having a distribution of the number of moles of alkylene oxide added within a narrow range can be prepared and the reaction product is little contaminated with unreacted starting material and by-products. Further, the catalyst can easily be eliminated from the reaction product.

Abstract translation: PCT No.PCT / JP94 / 02098 Sec。 371日期1995年8月21日 102（e）日期1995年8月21日PCT 1994年12月14日PCT PCT。 公开号WO95 / 17248 日期：1995年6月29日包含金属氧化物的烷氧基化催化剂，其碱度点以pKa值为9〜25表示，酸度点以50〜500μmol/ g的氨气吸附量表示， 使用该催化剂的烷氧基化物。 根据本发明，可以制备具有在窄范围内加入的环氧烷烃的摩尔数分布的烷氧基化物，并且反应产物很少被未反应的起始原料和副产物污染。 此外，催化剂可以容易地从反应产物中除去。

公开(公告)号：US5592415A

公开(公告)日：1997-01-07

申请号：US164780

申请日：1993-12-10

Applicant: Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

Inventor： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC: G11C8/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C13/00

CPC classification number: G11C16/0416 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C8/08 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

Abstract: Each memory cell of a non-volatile semiconductor memory essentially consisting of a one-transistor type memory cell comprising only of an MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

Abstract translation: 非易失性半导体存储器的每个存储单元基本上由仅包括具有浮置栅电极的MOSFET的单晶体管型存储单元组成。 当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。 当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。 可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。 特别是由于用于字线的负电压，可以降低编程数据时的漏极电压，从而可以减轻沟道部分的栅极氧化膜的劣化。

公开(公告)号：US5532971A

公开(公告)日：1996-07-02

申请号：US354639

申请日：1994-12-13

Applicant: Toshihiro Tanaka ,  Masataka Kato ,  Keiichi Yoshida ,  Hitoshi Kume ,  Yoshinobu Nakagome ,  Katsutaka Kimura

Inventor： Toshihiro Tanaka ,  Masataka Kato ,  Keiichi Yoshida ,  Hitoshi Kume ,  Yoshinobu Nakagome ,  Katsutaka Kimura

IPC: G11C17/00 ,  G11C8/08 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12 ,  G11C8/00 ,  G11C11/34

CPC classification number: G11C8/08 ,  G11C16/08 ,  G11C16/12

Abstract: An arrangement is provided to enhance the speed in the operation of erasing and programming of a nonvolatile semiconductor memory that is driven by a single supply voltage and to reduce the number of transistors making up the subword decoder circuit thereby minimizing the size of the device. For this purpose, in the subword decoder circuits WDi1-WDij that drive the word lines Wi1-Wij, the block selection address lines Bip and Bin generated from the first address line group are used as supply voltages for the inverter circuit that controls the voltage of the word line, and the gate selection address line Gj generated from the second address line group is used a gate input line.

Abstract translation: 提供了一种布置，以提高由单个电源电压驱动的非易失性半导体存储器的擦除和编程操作的速度，并且减少构成子字解码器电路的晶体管的数量，从而使器件的尺寸最小化。 为此，在驱动字线Wi1-Wij的子字解码器电路WDi1-WDij中，将从第一地址线组产生的块选择地址线Bip和Bin用作控制电压的逆变器电路的电源电压 字线和从第二地址线组产生的选通选择地址线Gj用于栅极输入线。

公开(公告)号：US5467309A

公开(公告)日：1995-11-14

申请号：US252604

申请日：1994-06-01

Applicant: Toshihiro Tanaka ,  Masataka Kato ,  Hitoshi Kume ,  Keisuke Ogura ,  Tetsuo Adachi

Inventor： Toshihiro Tanaka ,  Masataka Kato ,  Hitoshi Kume ,  Keisuke Ogura ,  Tetsuo Adachi

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/06

CPC classification number: G11C16/10

Abstract: A semiconductor nonvolatile memory device capable of reducing the overhead time of the time required for switching the verify operation and the verify operation itself. In the semiconductor nonvolatile memory device which operates to program the threshold of the memory cells on the basis of a plurality of repetitive operations, the mincing width .increment.Vth of the variation of the threshold of the memory cells relative to one operation for changing the threshold (applying the program pulse) is expressed by .increment.Vth=Kvth.multidot.log (t2/t1), and the ratio (t2/t1) between the program pulse widths is expressed by (t2/t1)=10E(.increment.Vth/Kvth). The pulses in which the difference .increment.Vth of the variation of the threshold of the memory cells is made constant, and the pulse width is increased as the repetition number increases are applied to the memory cells, thereby reducing the application number of program pulses.

Abstract translation: 一种半导体非易失性存储器件，其能够减少切换验证操作和验证操作本身所需的时间的开销时间。 在基于多个重复操作对存储器单元的阈值进行编程的半导体非易失性存储器件中，存储单元的阈值相对于用于改变阈值的一个操作的变化的切割宽度INCREMENT Vth 应用编程脉冲）由INCREMENT Vth = Kvthxlog（t2 / t1）表示，并且编程脉冲宽度之间的比率（t2 / t1）由（t2 / t1）= 10E（INCREMENT Vth / Kvth）表示。 使存储器单元的阈值的变化的差INCREMENT Vth变为恒定，并且脉冲宽度随着重复数量的增加而增加，从而减少编程脉冲的应用次数。