公开(公告)号：US06480418B2

公开(公告)日：2002-11-12

申请号：US09951979

申请日：2001-09-14

申请人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

发明人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

IPC分类号： G11C1604

CPC分类号： G11C16/0416 ,  G11C16/24 ,  G11C16/30

摘要： The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.

摘要翻译： 本发明提出了一种非易失性半导体存储器，包括多个主位线，连接到主位线的多个子位线以及多个存储单元阵列，每个存储单元阵列包括多个非易失性半导体存储器 细胞排列成阵列。 这些存储单元中的每一个具有源极端子，漏极端子和控制栅极，并且每个源极 - 漏极路径连接到子位线。 在主位线和连接到主位线的子位线之间设置第一晶体管的源极 - 漏极路径，并且第二晶体管的源极 - 漏极路径连接到子位线。

公开(公告)号：US06307780B1

公开(公告)日：2001-10-23

申请号：US09627411

申请日：2000-07-27

申请人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

发明人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

IPC分类号： G11C700

CPC分类号： G11C16/0416 ,  G11C16/24 ,  G11C16/30

摘要： The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.

摘要翻译： 本发明提出了一种非易失性半导体存储器，包括多个主位线，连接到主位线的多个子位线以及多个存储单元阵列，每个存储单元阵列包括多个非易失性半导体存储器 细胞排列成阵列。 这些存储单元中的每一个具有源极端子，漏极端子和控制栅极，并且每个源极 - 漏极路径连接到子位线。 在主位线和连接到主位线的子位线之间设置第一晶体管的源极 - 漏极路径，并且第二晶体管的源极 - 漏极路径连接到子位线。

公开(公告)号：US6122196A

公开(公告)日：2000-09-19

申请号：US219435

申请日：1998-12-23

申请人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

发明人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/24 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/24 ,  G11C16/30

摘要： The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.

摘要翻译： 本发明提出了一种非易失性半导体存储器，包括多个主位线，连接到主位线的多个子位线以及多个存储单元阵列，每个存储单元阵列包括多个非易失性半导体存储器 细胞排列成阵列。 这些存储单元中的每一个具有源极端子，漏极端子和控制栅极，并且每个源极 - 漏极路径连接到子位线。 在主位线和连接到主位线的子位线之间设置第一晶体管的源极 - 漏极路径，并且第二晶体管的源极 - 漏极路径连接到子位线。

公开(公告)号：US20110215401A1

公开(公告)日：2011-09-08

申请号：US12980675

申请日：2010-12-29

申请人： Kenji MIYAKOSHI ,  Shinichiro Wada ,  Yohei Yanagida ,  Takayuki Oshima ,  Keigo Kitazawa

发明人： Kenji MIYAKOSHI ,  Shinichiro Wada ,  Yohei Yanagida ,  Takayuki Oshima ,  Keigo Kitazawa

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/772 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7824

摘要： In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.

摘要翻译： 在LDMOS晶体管中，沟道长度减小以增加饱和电流，而不会导致在导通电阻和截止状态击穿电压之间的权衡方面优化的截止状态击穿电压。 在元件隔离膜和其中形成沟道的低浓度体区域中选择性地形成短沟道区域，使得短沟道区域位于栅极氧化膜的正下方。 短沟道区域具有与低浓度体区域相反的导电类型，并且其载流子浓度高于低浓度体区域的载流子浓度。 身体区域通过短通道区域的存在朝向高浓度源区域而退回。

公开(公告)号：US07459786B2

公开(公告)日：2008-12-02

申请号：US11155272

申请日：2005-06-17

申请人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Kensuke Ishikawa ,  Osamu Inoue ,  Takayuki Oshima

发明人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Kensuke Ishikawa ,  Osamu Inoue ,  Takayuki Oshima

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the multilayer wiring structure, a first insulation layer having a high barrier property and a compression stress, and making contact with the upper surface of a first wiring made of copper as a main component material, a second insulation film having a tensile stress, and a third insulation film having a dielectric constant which is lower than those of the first and second insulation film, are laminated one upon another in the mentioned order as viewed the bottom thereof, and a via hole is formed piercing through the first insulation film, the second insulation film and the third insulation film, making contact with the first wiring.

摘要翻译： 具有由铜作为主要成分材料形成的多层布线结构的可靠的半导体器件，其限制由应力迁移引起的空隙的发生。 在多层布线结构体中，具有高阻隔性和压缩应力的第一绝缘层，与由铜作为主要成分材料的第一布线的上表面接触，具有拉伸应力的第二绝缘膜，以及 具有低于第一绝缘膜和第二绝缘膜的介电常数的第三绝缘膜按照从底部开始的顺序依次层叠，并且形成穿过第一绝缘膜的通孔， 第二绝缘膜和第三绝缘膜，与第一布线接触。

公开(公告)号：US07323781B2

公开(公告)日：2008-01-29

申请号：US10807222

申请日：2004-03-24

申请人： Junji Noguchi ,  Takayuki Oshima ,  Noriko Miura ,  Kensuke Ishikawa ,  Tomio Iwaskai ,  Kiyomi Katsuyama ,  Tatsuyuki Saito ,  Tsuyoshi Tamaru ,  Hizuru Yamaguchi

发明人： Junji Noguchi ,  Takayuki Oshima ,  Noriko Miura ,  Kensuke Ishikawa ,  Tomio Iwaskai ,  Kiyomi Katsuyama ,  Tatsuyuki Saito ,  Tsuyoshi Tamaru ,  Hizuru Yamaguchi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76811 ,  H01L21/314 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76822 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

摘要翻译： 提高了布线的可靠性，其中包括以铜为主要成分的主导电膜。 在包括用作下层布线的布线的上表面的绝缘膜上形成由铜阻隔性优异的碳氮化硅膜形成的绝缘膜; 在绝缘膜上形成由与低介电常数材料膜具有优异粘合性的碳化硅膜形成的绝缘膜; 在绝缘膜上形成由作为层间绝缘膜的低介电常数材料形成的绝缘膜; 然后形成作为上层布线的布线。

公开(公告)号：US20070004189A1

公开(公告)日：2007-01-04

申请号：US11516762

申请日：2006-09-07

申请人： Junji Noguchi ,  Hideo Aoki ,  Shoji Hotta ,  Takayuki Oshima

发明人： Junji Noguchi ,  Hideo Aoki ,  Shoji Hotta ,  Takayuki Oshima

IPC分类号： H01L21/44

CPC分类号： H01L21/76811 ,  H01L21/02052 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76813

摘要： The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.

摘要翻译： 本发明提供了一种在双镶嵌工艺中使用氧化铝掩模用于干法蚀刻由SiOC膜构成的层间绝缘膜时形成通孔的缺陷的方法，其中在形成过孔之前形成通孔 接线沟。 也就是说，在通过盖绝缘体由低k SiOC膜构成的层间绝缘体上形成氧化铝掩模之后，使用光致抗蚀剂膜作为掩模对盖绝缘体和层间绝缘体进行干蚀刻以形成通孔。 接下来，在除去光致抗蚀剂膜之后，通过使用稀氢氟酸溶液来清洁通孔的内部以除去氧化铝残留物。 此后，使用氧化铝掩模作为掩模来干蚀刻帽绝缘体和层间绝缘体以形成布线沟槽。

公开(公告)号：US20060006543A1

公开(公告)日：2006-01-12

申请号：US11155272

申请日：2005-06-17

申请人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Kensuke Ishikawa ,  Osamu Inoue ,  Takayuki Oshima

发明人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Kensuke Ishikawa ,  Osamu Inoue ,  Takayuki Oshima

IPC分类号： H01L23/48

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the multilayer wiring structure, a first insulation layer having a high barrier property and a compression stress, and making contact with the upper surface of a first wiring made of copper as a main component material, a second insulation film having a tensile stress, and a third insulation film having a dielectric constant which is lower than those of the first and second insulation film, are laminated one upon another in the mentioned order as viewed the bottom thereof, and a via hole is formed piercing thorough the first insulation film, the second insulation film and the third insulation film, making contact with the first wiring.

摘要翻译： 具有由铜作为主要成分材料形成的多层布线结构的可靠的半导体器件，其限制由应力迁移引起的空隙的发生。 在多层布线结构体中，具有高阻隔性和压缩应力的第一绝缘层，与由铜作为主要成分材料的第一布线的上表面接触，具有拉伸应力的第二绝缘膜，以及 介电常数低于第一绝缘膜和第二绝缘膜的介电常数的第三绝缘膜按照其底部的顺序一个接一个层叠，并且形成穿过第一绝缘膜的通孔， 第二绝缘膜和第三绝缘膜，与第一布线接触。

公开(公告)号：US20050118809A1

公开(公告)日：2005-06-02

申请号：US10981662

申请日：2004-11-05

申请人： Junji Noguchi ,  Hideo Aoki ,  Shoji Hotta ,  Takayuki Oshima

发明人： Junji Noguchi ,  Hideo Aoki ,  Shoji Hotta ,  Takayuki Oshima

IPC分类号： H01L21/3065 ,  H01L21/28 ,  H01L21/304 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76811 ,  H01L21/02052 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76813

摘要： The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.

摘要翻译： 本发明提供了一种在双镶嵌工艺中使用氧化铝掩模用于干法蚀刻由SiOC膜构成的层间绝缘膜时形成通孔的缺陷的方法，其中在形成过孔之前形成通孔 接线沟。 也就是说，在通过盖绝缘体由低k SiOC膜构成的层间绝缘体上形成氧化铝掩模之后，使用光致抗蚀剂膜作为掩模对盖绝缘体和层间绝缘体进行干蚀刻以形成通孔。 接下来，在除去光致抗蚀剂膜之后，通过使用稀氢氟酸溶液来清洁通孔的内部以除去氧化铝残留物。 此后，使用氧化铝掩模作为掩模来干蚀刻帽绝缘体和层间绝缘体以形成布线沟槽。

公开(公告)号：US06266978B1

公开(公告)日：2001-07-31

申请号：US09392427

申请日：1999-09-09

申请人： Takayuki Oshima ,  Akira Fujinoki ,  Hiroyuki Nishimura ,  Yasuyuki Yaginuma

发明人： Takayuki Oshima ,  Akira Fujinoki ,  Hiroyuki Nishimura ,  Yasuyuki Yaginuma

IPC分类号： C03B3200

CPC分类号： C03C23/0025 ,  C03C3/06 ,  C03C23/002 ,  C03C2201/50

摘要： A simple method for producing a synthetic quartz glass having excellent homogeneity and high transmittance, which is useful as an optical material in producing steppers equipped with an ArF excimer laser as a radiation source. A method for producing a synthetic quartz glass for use in ArF excimer laser lithography, which comprises irradiating a highly homogeneous synthetic quartz glass containing less than 60 ppb of Na with ultraviolet radiation having a maximum wavelength of 260 nm for not less than the duration expressed by the equation: Y=(80X−1880)/Z wherein X represents an Na concentration (ppb), Y represents the duration of irradiation (hours), and Z represents the illuminance of an ultraviolet radiation on an irradiated surface (mW/cm2).

摘要翻译： 用于制造具有优异的均匀性和高透射率的合成石英玻璃的简单方法，其可用作制备装备有ArF准分子激光器作为辐射源的步进机中的光学材料。 一种用于制造用于ArF准分子激光光刻的合成石英玻璃的方法，其包括：将含有小于60ppb的Na的高度均匀的合成石英玻璃与最大波长为260nm的紫外线辐射照射不少于由 方程式：其中X表示Na浓度（ppb），Y表示照射持续时间（小时），Z表示照射表面上的紫外线照射的照度（mW / cm 2）。