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26 条记录 (耗时 0.036 秒)

    Manufacturing method of semiconductor device
    21.
    发明授权
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US07186575B2

    公开(公告)日：2007-03-06

    申请号：US11064500

    申请日：2005-02-23

    申请人： Daisuke Ito ,  Toshimi Kawahara

    发明人： Daisuke Ito ,  Toshimi Kawahara

    IPC分类号： H01L31/26 ,  H01L21/66

    CPC分类号： H01L22/22 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/11 ,  H01L2924/00014

    摘要： In a method for manufacturing a semiconductor device by processing of a wafer level, in the case of forming the semiconductor device at the wafer level, on the basis of inspection results on individual semiconductor chips constituting a semiconductor wafer, a treatment for forming a circuit including a rewiring pattern is performed with respect to a semiconductor chip judged as a conforming product and a treatment in which a rewiring pattern is not formed in order to avoid having adverse influence on a semiconductor device of a conforming product or an inspection apparatus in an inspection of a formed semiconductor device after forming the semiconductor device is performed with respect to a semiconductor chip judged as a nonconforming product.

    摘要翻译： 在通过晶片级的处理制造半导体器件的方法中，在基于晶片级形成半导体器件的情况下，基于构成半导体晶片的各个半导体芯片的检查结果，形成电路的处理包括 对于被判定为符合产品的半导体芯片和未形成重新布线图案的处理来执行重新布线图案，以避免对符合产品的半导体器件或检查装置的检查产生不利影响 相对于被判定为不合格品的半导体芯片进行形成半​​导体器件后的形成的半导体器件。

    Semiconductor device and method for fabricating it, and semiconductor sealing resin composition
    24.
    发明授权
    Semiconductor device and method for fabricating it, and semiconductor sealing resin composition 失效
    半导体装置及其制造方法以及半导体密封树脂组合物

    公开(公告)号：US06361879B1

    公开(公告)日：2002-03-26

    申请号：US09381765

    申请日：1999-09-23

    申请人： Yasuaki Tsutsumi ,  Masayuki Tanaka ,  Toshimi Kawahara ,  Yukio Takigawa

    发明人： Yasuaki Tsutsumi ,  Masayuki Tanaka ,  Toshimi Kawahara ,  Yukio Takigawa

    IPC分类号： H01L2912

    CPC分类号： H01L23/3114 ,  C08L63/00 ,  H01L23/293 ,  H01L23/3107 ,  H01L2224/274 ,  H01L2924/01019 ,  H01L2924/3511 ,  Y10T428/12528 ,  C08L61/04

    摘要： A sealed semiconductor chip having a surface film of a sealed resin composition, wherein the resin composition has a linear expansion coefficient of 60×10−6/K or less at a temperature equal to or less than its glass transition point and 140×10−6/K or less at a temperature equal to or higher than its glass transition point; a semiconductor-sealing resin composition for sealing a semiconductor chip, which has a linear expansion coefficient of 60×10−6/K or less at a temperature equal to or less than its glass transition point and 140×10−6/K or less at a temperature equal to or higher than its glass transition point; the sealed semiconductor chip is chip size and has high reliability; the semiconductor-sealing resin composition creates a good seal on chip wafers and has high reliability; and the chip wafers sealed with a surface film of the resin composition warp little.

    摘要翻译： 一种具有密封树脂组合物的表面膜的密封半导体芯片，其中，在等于或小于其玻璃化转变点和140×10 -6 / K的温度下，树脂组合物的线性膨胀系数为60×10 -6 / K以下，或者 在等于或高于其玻璃化转变点的温度下较少; 用于密封半导体芯片的半导体密封树脂组合物，其在等于或小于其玻璃化转变点的温度下为线性膨胀系数为60×10 -6 / K或更小，在等于或等于140×10 -6 / K 达到或高于其玻璃化转变点; 密封半导体芯片芯片尺寸大，可靠性高; 半导体密封树脂组合物在芯片晶片上形成良好的密封并具有高可靠性; 并且用树脂组合物的表面膜密封的芯片晶片变小。

    Probe card and method of testing wafer having a plurality of semiconductor devices
    26.
    发明授权
    Probe card and method of testing wafer having a plurality of semiconductor devices 有权
    探针卡和测试具有多个半导体器件的晶片的方法

    公开(公告)号：US06563330B1

    公开(公告)日：2003-05-13

    申请号：US09540870

    申请日：2000-03-31

    申请人： Shigeyuki Maruyama ,  Daisuke Koizumi ,  Naoyuki Watanabe ,  Yoshito Konno ,  Eiji Yoshida ,  Toshiyuki Honda ,  Toshimi Kawahara ,  Kenichi Nagashige

    发明人： Shigeyuki Maruyama ,  Daisuke Koizumi ,  Naoyuki Watanabe ,  Yoshito Konno ,  Eiji Yoshida ,  Toshiyuki Honda ,  Toshimi Kawahara ,  Kenichi Nagashige

    IPC分类号： G01R3102

    CPC分类号： G01R31/2886 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/11 ,  H05K3/326

    摘要： A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board. Displacements of the internal terminal resulting from the temperature load applied during testing of the wafer are compensated by the level transitioning portion of the first wiring. Unevenness involved with the contact between the contact electrodes on the probe card and the electrodes on the chips are compensated by the contact electrodes and/or elastic material according to the present invention. An electrode pitch of the contact electrodes is expanded by the first wiring.

    摘要翻译： 一种用于测试形成多个半导体芯片的晶片的探针卡，所述探针卡包括基板和多层基板。 探针卡还可以包括柔性基底。 在其中一个芯片上与电极相对设置的接触电极设置在柔性基板的上方或下方，或者可以设置在多层基板上的弹性材料上。 第一布线具有连接到接触电极的第一部分，从第一部分的电平延伸到较低电平的多层基板的电平转换部分，以及连接到电平转换部分的端部处的连接端子 多层基板上的内部端子。 多层基板中的第二布线将内部端子连接到多层基板的外围的外部端子。 电路板上的第三个接线将多层基板上的外部端子连接到电路板上的外部连接端子。 在晶片测试期间施加的温度负载导致的内部端子的位移由第一布线的电平转换部分补偿。 涉及探针卡上的接触电极和芯片上的电极之间的接触的不均匀性由根据本发明的接触电极和/或弹性材料补偿。 接触电极的电极间距由第一布线扩大。