公开(公告)号：US5099146A

公开(公告)日：1992-03-24

申请号：US539828

申请日：1990-06-18

申请人： Takahiro Miki ,  Shiro Hosotani ,  Toshio Kumamoto

发明人： Takahiro Miki ,  Shiro Hosotani ,  Toshio Kumamoto

IPC分类号： H01L29/78 ,  H03K3/22 ,  H03K5/08 ,  H03K17/30 ,  H03K17/687 ,  H03M1/36

CPC分类号： H03K5/086 ,  H01L2924/0002

摘要： In a controlled threshold type electric device having first and second transistors and a differential amplifier which receives a reference input voltage, a voltage corresponding to the threshold voltage of the first transistor itself is applied to the differential amplifier as a feedback input voltage. The differential amplifier compares the received feed back input voltage with the reference input voltage and applies a control voltage to the backgate of the first transistor so that the threshold value of the first transistor converges to a desired value. This control voltage is also applied to the backgate of the second transistor so that the threshold voltage of the second transistor also converges to a desired value. Since the voltage corresponding to the threshold value of the first transistor is applied to the differential amplifier, an accurate feed back control is made. Further, since the differential amplifier can be manufactured through the MOS standard process, the manufacturing cost can be reduced.

摘要翻译： 在具有第一和第二晶体管的受控阈值型电器件和接收参考输入电压的差分放大器中，将与第一晶体管本身的阈值电压相对应的电压作为反馈输入电压施加到差分放大器。 差分放大器将接收的反馈输入电压与参考输入电压进行比较，并将控制电压施加到第一晶体管的背栅极，使得第一晶体管的阈值收敛到期望值。 该控制电压也被施加到第二晶体管的背栅，使得第二晶体管的阈值电压也收敛到期望值。 由于将对应于第一晶体管的阈值的电压施加到差分放大器，因此进行精确的反馈控制。 此外，由于可以通过MOS标准工艺制造差分放大器，所以可以降低制造成本。

公开(公告)号：US08223050B2

公开(公告)日：2012-07-17

申请号：US12911345

申请日：2010-10-25

申请人： Takashi Matsumoto ,  Toshio Kumamoto ,  Takashi Okuda

发明人： Takashi Matsumoto ,  Toshio Kumamoto ,  Takashi Okuda

IPC分类号： H03M1/20

CPC分类号： H03M3/332 ,  H03M1/00 ,  H03M1/0641 ,  H03M1/12 ,  H03M3/30 ,  H03M3/43 ,  H03M3/452 ,  H03M3/454

摘要： In a delta-sigma A/D converter provided with plural channels for converting an analog input signal into a digital signal, an adverse influence of an idle tone is reduced in each channel. The delta-sigma A/D converter comprises: a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.

摘要翻译： 在具有用于将模拟输入信号转换为数字信号的多个通道的Δ-ΣA / D转换器中，在每个通道中降低了空闲音调的不利影响。 Δ-ΣA / D转换器包括：量化并输出接收信号的第一量化器; 第一D / A转换器，其将第一量化器的输出信号转换为模拟信号，并输出转换的模拟信号; 第一操作单元，其输出表示第一模拟输入信号和第一D / A转换器的输出信号的差的信号; 第一积分器，其对第一运算单元的输出信号进行积分并输出积分信号; 产生第一抖动信号的第一抖动电路; 以及第二操作单元，其将第一抖动信号添加到第一积分器的输出信号，并将相加的信号输出到第一量化器。

公开(公告)号：US08188526B2

公开(公告)日：2012-05-29

申请号：US12958923

申请日：2010-12-02

申请人： Takashi Okuda ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Toshio Kumamoto

IPC分类号： H01L27/08 ,  H01L29/94

CPC分类号： H01L23/585 ,  H01L27/0248 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.

摘要翻译： 本发明的目的是确保将模拟块中的预定半导体元件或预定半导体元件组与数字块产生的噪声保护起来。 根据本发明的半导体器件包括半导体衬底，作为形成数字电路的区域的数字块和形成模拟电路的区域的模拟块，通过将模拟电路的上表面 半导体基板和设置在半导体基板上的基板电位固定区域，以在平面图中包围模拟块中的预定半导体元件组，以及连接到基板电位固定区域并从外部接收预定电位的焊盘 部分。

公开(公告)号：US07915708B2

公开(公告)日：2011-03-29

申请号：US12485528

申请日：2009-06-16

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。

公开(公告)号：US07868413B2

公开(公告)日：2011-01-11

申请号：US12267166

申请日：2008-11-07

申请人： Takashi Okuda ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Toshio Kumamoto

IPC分类号： H01L21/762

CPC分类号： H01L23/585 ,  H01L27/0248 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.

摘要翻译： 本发明的目的是确保将模拟块中的预定半导体元件或预定半导体元件组与数字块产生的噪声保护起来。 根据本发明的半导体器件包括半导体衬底，作为形成数字电路的区域的数字块和形成模拟电路的区域的模拟块，通过将模拟电路的上表面 半导体基板和设置在半导体基板上的基板电位固定区域，以在平面图中包围模拟块中的预定半导体元件组，以及连接到基板电位固定区域并从外部接收预定电位的焊盘 部分。

公开(公告)号：US20080116526A1

公开(公告)日：2008-05-22

申请号：US12007496

申请日：2008-01-11

申请人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

发明人： Hiroyuki Amishiro ,  Toshio Kumamoto ,  Motoshige Igarashi ,  Kenji Yamaguchi

IPC分类号： H01L27/06

CPC分类号： H01L27/0207 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20

摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.

摘要翻译： 本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。 有源区靠近电阻元件配置。 这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

公开(公告)号：US06538589B2

公开(公告)日：2003-03-25

申请号：US10136416

申请日：2002-05-02

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Yasuo Morimoto

IPC分类号： H03M300

CPC分类号： H03M7/3006 ,  H03M7/302

摘要： A digital &Dgr;&Sgr; modulator comprises a first-stage 1-bit &Dgr;&Sgr; modulator provided with an 1-bit (1 is an arbitrary natural number) quantizer, for modulating digital data, a correction logic for multiplying a quantization error caused in the 1-bit quantizer by a correction so that the quantization error caused in the 1-bit quantizer is eliminated at an output of the first-stage 1-bit &Dgr;&Sgr; modulator, and a next-stage m-bit &Dgr;&Sgr; modulator provided with an m-bit (m is an arbitrary natural number larger than 1) quantizer, for modulating and feeding the quantization error which is multiplied by the correction by the correction logic back to the first-stage 1-bit &Dgr;&Sgr; modulator.

摘要翻译： 一个数字DELTASIGMA调制器包括一个第一级1位DELTASIGMA调制器，它配备1位（1为任意自然数）量化器，用于调制数字数据;一个校正逻辑，用于将1位量化器中引起的量化误差相乘 通过校正，使得在第一级1位DELTASIGMA调制器的输出处消除在1位量化器中引起的量化误差，并且提供具有m位的下一级m位DELTASIGMA调制器（m是 大于1）量化器的任意自然数，用于将与校正逻辑的校正相乘的量化误差调制和馈送回到第一级1位DELTASIGMA调制器。

公开(公告)号：US5821893A

公开(公告)日：1998-10-13

申请号：US740520

申请日：1996-10-30

申请人： Toshio Kumamoto ,  Osamu Matsumoto

发明人： Toshio Kumamoto ,  Osamu Matsumoto

IPC分类号： H03M1/14 ,  H03M1/06 ,  H03M1/16 ,  H03M1/38

CPC分类号： H03M1/0695 ,  H03M1/167

摘要： In a pipeline type A/D converter, a switch for sampling an analog potential signal has its other terminal in connection with an A/D converter, a D/A converter, a capacitor for subtraction. Even when frequency of the analog potential signal is raised such that input current is increased and a voltage drop is increased at the switch, there will be no error in the result of subtraction like in the conventional example where analog potential signal was directly input to A/D converter. Accordingly, a pipeline type A/D converter with low power dissipation and satisfactory frequency characteristics is obtained.

摘要翻译： 在流水线型A / D转换器中，用于对模拟电位信号采样的开关具有与A / D转换器，D / A转换器，用于减法的电容器相连的另一端。 即使在模拟电位信号的频率升高使得输入电流增加并且在开关处电压降增加的情况下，与在将模拟电位信号直接输入到A的常规示例中一样，减法结果将不会有误差 / D转换器。 因此，获得具有低功耗和令人满意的频率特性的流水线型A / D转换器。

公开(公告)号：US5146201A

公开(公告)日：1992-09-08

申请号：US721865

申请日：1991-06-26

申请人： Masatoshi Kimura ,  Toshio Kumamoto

发明人： Masatoshi Kimura ,  Toshio Kumamoto

IPC分类号： G01R33/07 ,  H01L43/06

CPC分类号： H01L43/065

摘要： A magnetic sensor system includes stacked substrates each including a respective Hall element for detecting mutually orthogonal magnetic fields. Each Hall device includes a semiconductor material formed as a rectangular solid in a central portion of an opposite conductivity type substrate. The semiconductor material is sandwiched in a first direction between a pair of current electrodes and sandwiched in a second direction orthogonal to the first direction between a pair of Hall voltage detecting electrodes. Multiple substrates are stacked to detect magnetic fields in three dimensions. An analog-to-digital converter is formed in an additional stacked substrate.

摘要翻译： 磁传感器系统包括堆叠的衬底，每个衬底包括用于检测相互正交的磁场的相应的霍尔元件。 每个霍尔器件包括在相反导电型衬底的中心部分中形成为矩形固体的半导体材料。 将半导体材料夹在一对电流电极之间的第一方向上，并夹在一对霍尔电压检测电极之间的与第一方向正交的第二方向上。 堆叠多个基板以检测三维的磁场。 模数转换器形成在附加的堆叠衬底中。

公开(公告)号：US07557427B2

公开(公告)日：2009-07-07

申请号：US11845339

申请日：2007-08-27

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L51/05

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对齐。