公开(公告)号：US06432799B1

公开(公告)日：2002-08-13

申请号：US09448979

申请日：1999-11-24

申请人： Takashi Hashimoto ,  Yoshifumi Ohnishi ,  Toshiyuki Kikuchi

发明人： Takashi Hashimoto ,  Yoshifumi Ohnishi ,  Toshiyuki Kikuchi

IPC分类号： H01L21762

CPC分类号： H01L21/8249 ,  H01L21/76202 ,  H01L21/76235 ,  H01L21/763

摘要： A method of manufacturing a semiconductor integrated circuit device according to this invention, comprises a step of forming in a semiconductor substrate a deep groove for trench isolation with an aspect ratio of greater than 1, a step of burying a first insulating film in the deep groove in such a way that a shallow groove with an aspect ratio of not greater than 1 remains, and a step of depositing a second insulating film over the semiconductor substrate and then removing the upper portion of the second insulating film to planarize the upper surface of the second insulating film buried in the shallow groove in such a way that the upper surface of the second insulating film is almost flush with the surface surrounding the shallow groove.

摘要翻译： 根据本发明的制造半导体集成电路器件的方法包括在半导体衬底中形成具有大于1的纵横比用于沟槽隔离的深槽的步骤，将第一绝缘膜埋入深沟槽 使得长宽比不大于1的浅槽保留，并且在半导体衬底上沉积第二绝缘膜，然后去除第二绝缘膜的上部以平坦化第二绝缘膜的上表面的步骤 第二绝缘膜埋入浅槽中，使得第二绝缘膜的上表面与围绕浅槽的表面几乎齐平。

公开(公告)号：US6149412A

公开(公告)日：2000-11-21

申请号：US366197

申请日：1999-08-04

申请人： Toshiyuki Kikuchi

发明人： Toshiyuki Kikuchi

IPC分类号： F04C18/02 ,  F01C17/06 ,  F16C19/10 ,  F16C33/58 ,  F04C18/00

CPC分类号： F01C17/06 ,  F16C19/50

摘要： A rotation preventing mechanism is composed of a thrust ball bearing including a first race section having an annular shape, a second race section disposed at an eccentric position in confrontation with the first race section at intervals and thrust balls interposed between the first and second race sections. The first and second race sections have ball accommodating grooves formed at the confronting surfaces thereof, respectively. Each of the ball accommodating grooves includes a central portion and a groove bottom portion around it. When the radius of curvature of each thrust ball is represented by RB, the radius of curvature of the groove bottom portion on an inner side is represented by Rin and the radius of curvature thereof in an outer side is represented by Rout, and the ball accommodating groove has a shape satisfying a formula RB.ltoreq.Rin

摘要翻译： 旋转防止机构由具有环状的第一座圈部的推力球轴承构成，设置在与第一座圈对置的偏心位置处的间隔的第二座圈部和插入在第一和第二座圈部之间的推力球 。 第一和第二座圈分别具有形成在其相对表面上的球容纳槽。 每个球容纳槽包括围绕其的中心部分和槽底部分。 当每个推力球的曲率半径由RB表示时，内侧的槽底部的曲率半径由Rin表示，外侧的曲率半径由Rout表示，球容纳 凹槽具有满足公式RB

公开(公告)号：US6133094A

公开(公告)日：2000-10-17

申请号：US123405

申请日：1998-07-28

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01C7/06 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L21/336

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US5846869A

公开(公告)日：1998-12-08

申请号：US685844

申请日：1996-07-24

申请人： Takashi Hashimoto ,  Hideo Miura ,  Toshiyuki Kikuchi ,  Toshiyuki Mine ,  Yoichi Tamaki ,  Takahiro Kumauchi

发明人： Takashi Hashimoto ,  Hideo Miura ,  Toshiyuki Kikuchi ,  Toshiyuki Mine ,  Yoichi Tamaki ,  Takahiro Kumauchi

IPC分类号： H01L29/73 ,  H01L21/205 ,  H01L21/306 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/732 ,  H01L29/737 ,  H01L21/301

CPC分类号： H01L21/02052 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/8222 ,  H01L29/66272 ,  H01L29/7375 ,  Y10S438/906

摘要： A method of manufacturing a bipolar transistor having an improved polysilicon emitter is disclosed. More specifically, hydrogen terminations or OH group terminations adhered (bonded) to an emitter-forming region are eliminated by a heat treatment in an inert gas atmosphere before forming emitter polysilicon. Subsequently, an amorphous silicon film for forming an emitter polysilicon is formed at a low temperature.

摘要翻译： 公开了一种制造具有改进的多晶硅发射极的双极晶体管的方法。 更具体地，在形成发射极多晶硅之前，通过在惰性气体气氛中的热处理来消除粘附（结合）到发射体形成区域的氢端基或OH基端基。 随后，在低温下形成用于形成发射极多晶硅的非晶硅膜。

公开(公告)号：US07909931B2

公开(公告)日：2011-03-22

申请号：US11729862

申请日：2007-03-30

申请人： Ryouhei Saito ,  Toshiyuki Kikuchi ,  Kiyoaki Misu ,  Kazuko Fukutani ,  Kazuyoshi Kato

发明人： Ryouhei Saito ,  Toshiyuki Kikuchi ,  Kiyoaki Misu ,  Kazuko Fukutani ,  Kazuyoshi Kato

IPC分类号： C30B27/00

CPC分类号： C30B15/10 ,  C30B15/30 ,  C30B29/06 ,  C30B35/002 ,  Y10S117/90 ,  Y10T117/10 ,  Y10T117/1032 ,  Y10T117/1052

摘要： The present invention provides a silica glass crucible for manufacturing a silicon single crystal, in which melt vibration can be controlled more certainly and a high yield of single crystal can be realized. A first substantially bubble-free layer 10a having a thickness of 100 μm-450 μm is formed on the inner periphery side of an initial melt line zone 10 which has a height of 10 mm-30 mm, of a transparent layer, a bubble-containing layer 10b having a thickness of 100 μm or more and bubbles with an average diameter of 20 μm-60 μm is formed outside the above-mentioned first substantially bubble-free layer 10a, and a second substantially bubble-free layer 10c having a thickness of 300 μm or more is formed on the inner periphery side in the whole region lower than the above-mentioned initial melt line zone 10.

摘要翻译： 本发明提供一种用于制造硅单晶的石英玻璃坩埚，其中可以更可靠地控制熔体振动并且可以实现高产率的单晶。 在透明层的高度为10mm-30mm的初始熔融线区10的内周侧形成厚度为100μm-450μm的第一基本上无气泡层10a， 在上述第一基本无气泡层10a的外侧形成具有100μm以上的厚度的平均粒径为20μm〜60μm的气泡的第二基本无气泡层10c， 在比上述初始熔融线区域10低的整个区域的内周侧上形成有300μm以上。

公开(公告)号：US06941086B2

公开(公告)日：2005-09-06

申请号：US10665479

申请日：2003-09-22

申请人： Toshiyuki Kikuchi

发明人： Toshiyuki Kikuchi

IPC分类号： G03G15/23 ,  G03G15/20 ,  G03G15/00

CPC分类号： G03G15/232

摘要： A photoreceptor transfers a first image to a first side of a paper, an intermediate transfer belt transfers a second image to a second side of the paper. The intermediate transfer belt also conveys the paper. A conveying unit directly conveys the paper, with the images, to a heating unit that fixes the images. The paper is slowly conveyed in the heating unit as compared to when it is conveyed by the belt.

摘要翻译： 感光器将第一图像传送到纸张的第一侧，中间转印带将第二图像传送到纸张的第二侧。 中间转印带也传送纸张。 传送单元将纸张与图像直接传送到固定图像的加热单元。 与通过带传送的纸相比，纸在加热单元中缓慢地传送。

公开(公告)号：US06835632B2

公开(公告)日：2004-12-28

申请号：US10460215

申请日：2003-06-13

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01L2120

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶硅层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US06649487B2

公开(公告)日：2003-11-18

申请号：US10046813

申请日：2002-01-17

申请人： Takashi Hashimoto ,  Yoshifumi Ohnishi ,  Toshiyuki Kikuchi

发明人： Takashi Hashimoto ,  Yoshifumi Ohnishi ,  Toshiyuki Kikuchi

IPC分类号： H01L2176

CPC分类号： H01L21/8249 ,  H01L21/76202 ,  H01L21/76235 ,  H01L21/763

摘要： A method of manufacturing a semiconductor integrated circuit device according to this invention, comprises a step of forming in a semiconductor substrate a deep groove for trench isolation with an aspect ratio of greater than 1, a step of burying a first insulating film in the deep groove in such a way that a shallow groove with an aspect ratio of not greater than 1 remains, and a step of depositing a second insulating film over the semiconductor substrate and then removing the upper portion of the second insulating film to planarize the upper surface of the second insulating film buried in the shallow groove in such a way that the upper surface of the second insulating film is almost flush with the surface surrounding the shallow groove.

公开(公告)号：US06524924B1

公开(公告)日：2003-02-25

申请号：US09123406

申请日：1998-07-28

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01L2120

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的至少两层结构，并且第一多晶硅层具有正电温度依赖性而第二 多晶层具有电阻的负温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US6027983A

公开(公告)日：2000-02-22

申请号：US455139

申请日：1995-05-31

申请人： Takashi Hashimoto ,  Yoshifumi Ohnishi ,  Toshiyuki Kikuchi

发明人： Takashi Hashimoto ,  Yoshifumi Ohnishi ,  Toshiyuki Kikuchi

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/08 ,  H01L27/12

CPC分类号： H01L21/8249 ,  H01L21/76202 ,  H01L21/76235 ,  H01L21/763

摘要： A method of manufacturing a semiconductor integrated circuit device according to this invention, comprises a step of forming in a semiconductor substrate a deep groove for trench isolation with an aspect ratio of greater than 1, a step of burying a first insulating film in the deep groove in such a way that a shallow groove with an aspect ratio of not greater than 1 remains, and a step of depositing a second insulating film over the semiconductor substrate and then removing the upper portion of the second insulating film to planarize the upper surface of the second insulating film buried in the shallow groove in such a way that the upper surface of the second insulating film is almost flush with the surface surrounding the shallow groove.

摘要翻译： 根据本发明的制造半导体集成电路器件的方法包括在半导体衬底中形成具有大于1的纵横比用于沟槽隔离的深槽的步骤，将第一绝缘膜埋入深沟槽 使得长宽比不大于1的浅槽保留，并且在半导体衬底上沉积第二绝缘膜，然后去除第二绝缘膜的上部以平坦化第二绝缘膜的上表面的步骤 第二绝缘膜埋入浅槽中，使得第二绝缘膜的上表面与围绕浅槽的表面几乎齐平。