公开(公告)号：US06448171B1

公开(公告)日：2002-09-10

申请号：US09565962

申请日：2000-05-05

申请人： Tsing-Chow Wang ,  Te-Sung Wu

发明人： Tsing-Chow Wang ,  Te-Sung Wu

IPC分类号： H01L2144

CPC分类号： H01L24/03 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

摘要： Within a method for fabricating a microelectronic fabrication, and a microelectronic fabrication fabricated employing the method, there is first provided a substrate. Within the method, there is then formed over the substrate a patterned bond pad layer. There is also formed over the substrate a patterned passivation layer which passivates a series of edges of the patterned bond pad layer while leaving exposed a central portion of the patterned bond pad layer, where the patterned passivation layer has a series of protrusions within the patterned passivation layer over the series of edges of the patterned bond pad layer. There is then formed over the central portion of the patterned bond pad layer and bridging over the series of protrusions of the patterned passivation layer a first terminal electrode layer having an upper surface which is concave. Finally, there is then formed over the first terminal electrode layer a second terminal electrode layer having an upper surface which is other than concave. The method otherwise contemplates the microelectronic fabrication fabricated employing the method. A terminal electrode structure which comprises the first terminal electrode layer and the second terminal electrode layer provides enhanced passivation of the microelectronic fabrication and enhanced bondability to the terminal electrode structure.

摘要翻译： 在用于制造微电子制造的方法和使用该方法制造的微电子制造中，首先提供了一种衬底。 在该方法中，然后在衬底上形成图案化的接合焊盘层。 在衬底上还形成图案化钝化层，其钝化图案化接合焊盘层的一系列边缘，同时留下图案化接合焊盘层的中心部分，其中图案化钝化层在图案化钝化层内具有一系列突起 在图案化接合焊盘层的一系列边缘上方。 然后形成在图案化接合焊盘层的中心部分上，并且桥接在图案化钝化层的一系列突起上，第一端电极层具有凹面的上表面。 最后，在第一端子电极层上形成具有不同于凹面的上表面的第二端子电极层。 该方法另外考虑使用该方法制造的微电子制造。 包括第一端子电极层和第二端子电极层的端子电极结构提供了微电子制造的增强的钝化和增强的对端子电极结构的可接合性。

公开(公告)号：US06424037B1

公开(公告)日：2002-07-23

申请号：US09941384

申请日：2001-08-28

申请人： Chung W Ho ,  Tsing-Chow Wang

发明人： Chung W Ho ,  Tsing-Chow Wang

IPC分类号： H01L2348

CPC分类号： H01L24/12 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/13647 ,  H01L2224/13671 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/1025 ,  H05K2201/2081 ,  H05K2203/0315 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00

摘要： Within a method for forming a solder interconnection structure for use within a microelectronic fabrication, there is first provided a substrate having formed thereover a bond pad. There is then formed upon the bond pad a first solder interconnection layer. There is then formed over the first solder interconnection layer an annular solder non-wettable copper oxide layer which does not cover an upper dome portion of the first solder interconnection layer. There is then formed over the upper dome portion of the first solder interconnection layer and not upon the annular solder non-wettable copper oxide layer a second solder interconnection layer.

公开(公告)号：US5414299A

公开(公告)日：1995-05-09

申请号：US126288

申请日：1993-09-24

申请人： Tsing-Chow Wang ,  Louis H. Liang

发明人： Tsing-Chow Wang ,  Louis H. Liang

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/60 ,  H01L23/48

CPC分类号： H01L23/4985 ,  H01L23/3157 ,  H01L23/49572 ,  H01L23/60 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/19041 ,  H01L2924/3025

摘要： A semiconductor device interconnect package assembly for TAB packages is disclosed having a central portion of material which is utilized as part of the package structure to provide scratch protection to the active surface of a semiconductor die and to the inner lead bonding areas. The central portion of material can be modified in various ways to improve the overall performance of the package, and to reduce stress generated in the TAB package due to thermal mismatch. The assembly also includes a plurality of apertures in the substrate film which overlap and expose a plurality of groups of inner lead portions. The plurality of apertures allows each group of exposed inner lead portions to be encapsulated independently from each other group. By encapsulating each of these groups separately, scratch protection is provided to the inner lead bonding areas while simultaneously reducing the stress on each of the leads due to the heating and cooling of the encapsulating material.

摘要翻译： 公开了一种用于TAB封装的半导体器件互连封装组件，其具有材料的中心部分，其被用作封装结构的一部分，以向半导体管芯的有源表面和内引线接合区域提供划痕保护。 材料的中心部分可以以各种方式进行修改以改善包装的整体性能，并且减少由于热失配而导致的TAB包装中产生的应力。 该组件还包括在衬底膜中的多个孔，其重叠并暴露多组内引线部分。 多个孔允许每组暴露的内引线部分彼此独立地被封装。 通过分别封装这些组中的每一个，由于封装材料的加热和冷却，同时减少了每个引线上的应力，从而在内引线接合区域提供划痕保护。

公开(公告)号：US4559459A

公开(公告)日：1985-12-17

申请号：US480524

申请日：1983-03-30

申请人： Tsing-Chow Wang ,  Richard M. Josephs

发明人： Tsing-Chow Wang ,  Richard M. Josephs

IPC分类号： H03K19/195

CPC分类号： H03K19/1954 ,  H03K19/1956 ,  Y10S505/859

摘要： A high gain Josephson junction logic circuit is provided. The novel circuit comprises a high gain non-linear threshold input Josephson junction logic circuit which is coupled to a high gain Josephson junction amplifier. The high gain input circuit provides the capability of driving a larger number of output circuits or employing a larger number of input signals.

摘要翻译： 提供高增益约瑟夫逊结逻辑电路。 该新颖电路包括耦合到高增益约瑟夫逊结放大器的高增益非线性阈值输入约瑟夫逊结逻辑电路。 高增益输入电路提供驱动更多数量的输出电路或采用更大数量的输入信号的能力。

公开(公告)号：US4458160A

公开(公告)日：1984-07-03

申请号：US323144

申请日：1981-11-19

申请人： Richard M. Josephs ,  Tsing-Chow Wang

发明人： Richard M. Josephs ,  Tsing-Chow Wang

IPC分类号： H03F19/00 ,  H03K3/38

CPC分类号： H03F19/00 ,  Y10S505/865

摘要： A single Josephson junction device is arranged in a single branch which comprises an external source resistor connected in series with an output resistor and a Josephson junction device. An input node and an input resistor are in series and connected to the node between the output resistor and the Josephson junction device. Voltage signals applied to the input voltage node are amplified by connecting a high gain voltage output in parallel with the output resistor and providing sensing means for sensing the voltage output across the output resistor only when the Josephson junction device is switching from its low impedance state to its high impedance state.

摘要翻译： 单个约瑟夫逊结装置布置在单个分支中，其包括与输出电阻器和约瑟夫逊结装置串联连接的外部源电阻器。 输入节点和输入电阻串联连接到输出电阻和约瑟夫逊结器件之间的节点。 施加到输入电压节点的电压信号通过与输出电阻并联连接高增益电压输出而被放大，并提供感测装置，用于只有当约瑟夫逊结器件从其低阻抗状态切换到 其高阻抗状态。

公开(公告)号：US4413196A

公开(公告)日：1983-11-01

申请号：US298148

申请日：1981-08-31

申请人： Richard M. Josephs ,  Tsing-Chow Wang

发明人： Richard M. Josephs ,  Tsing-Chow Wang

IPC分类号： H03K19/195

CPC分类号： H03K19/1956 ,  Y10S505/859

摘要： A two branch, three Josephson junction gating circuit is provided with a plurality of inputs to enable the circuit to be operated as a high-gain logic OR gate. The circuit is arranged to provide a larger operating window area and to provide an improved and optimized gain characteristic by selectively switching ON the Josephson junctions in the circuit.

摘要翻译： 两个分支，三个约瑟夫逊结门控门电路设置有多个输入，以使电路能够作为高增益逻辑或门运行。 电路被设置成提供更大的操作窗口面积并且通过选择性地接通电路中的约瑟夫逊结来提供改进和优化的增益特性。