公开(公告)号：US10020274B2

公开(公告)日：2018-07-10

申请号：US15611804

申请日：2017-06-02

Applicant: TETOS Co., Ltd.

Inventor： Woo Young Ahn ,  Seong Wan Park

IPC: B23K35/00 ,  B23K35/02 ,  B23K35/22 ,  H01L23/00 ,  B23K35/26

CPC classification number: H01L24/13 ,  B23K35/0244 ,  B23K35/262 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Disclosed is a solder particle including a plastic core; a copper-free metal layer which is formed on an external surface of the plastic core; and a solder layer which is formed on the copper-free metal layer and contains not less than 85 wt % tin. Thus, it is possible to provide a solder particle with a copper-free metal layer, which is excellent in strength and conductivity and prevents or minimizes generation of a void during a reflow process or the like.

公开(公告)号：US09496235B2

公开(公告)日：2016-11-15

申请号：US14466877

申请日：2014-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chieh Hsieh ,  Cheng-Lin Huang ,  Po-Hao Tsai ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11616 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13013 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1362 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/16056 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81121 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/384 ,  H01L2924/3841 ,  H01L2924/00014

Abstract: A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.

Abstract translation: 提供了一种用于导电柱的系统和方法。 一个实施例包括具有位于其外边缘周围的沟槽的导电柱。 当在导电柱上形成导电凸块时，沟槽用于引导诸如焊料的导电材料。 导电柱然后可以通过导电材料电连接到另一接触件。

公开(公告)号：US08659161B2

公开(公告)日：2014-02-25

申请号：US13165599

申请日：2011-06-21

Applicant: Ashok V. Krishnamoorthy ,  Craig A. Stephen ,  John E. Cunningham ,  James G. Mitchell

Inventor： Ashok V. Krishnamoorthy ,  Craig A. Stephen ,  John E. Cunningham ,  James G. Mitchell

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L23/48 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/81097 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81815 ,  H01L2224/81855 ,  Y10T428/24479 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01082 ,  H01L2924/0105

Abstract: A chip package includes a substrate having a positive feature, which is defined on a surface of the substrate and which protrudes above a region on the surface proximate to the positive feature. Furthermore, the chip package includes a mechanical reinforcement mechanism defined on the substrate proximate to the positive feature that increases a lateral shear strength of the positive feature relative to the substrate. In this way, the chip package may facilitate increased reliability of a multi-chip module (MCM) that includes the chip package.

Abstract translation: 芯片封装包括具有正特征的衬底，其被限定在衬底的表面上并且突出在接近正特征的表面上的区域上方。 此外，芯片封装包括限定在靠近正特征的基板上的机械加强机构，其增加正特征相对于基板的横向剪切强度。 以这种方式，芯片封装可以有助于增加包括芯片封装的多芯片模块（MCM）的可靠性。

公开(公告)号：US08623763B2

公开(公告)日：2014-01-07

申请号：US13150899

申请日：2011-06-01

Applicant: Jeffrey Alan West

Inventor： Jeffrey Alan West

IPC: H01L21/44

CPC classification number: H01L23/538 ,  H01L21/563 ,  H01L23/481 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2224/13681 ,  H01L2224/14181 ,  H01L2224/1613 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01074

Abstract: A method of protecting through substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips. The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head. The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips.

公开(公告)号：US20120299197A1

公开(公告)日：2012-11-29

申请号：US13478613

申请日：2012-05-23

Applicant: Heungkyu KWON ,  Kang Joon Lee ,  Jae Wook Yoo ,  Su-Chang Lee

Inventor： Heungkyu KWON ,  Kang Joon Lee ,  Jae Wook Yoo ,  Su-Chang Lee

IPC: H01L23/48

CPC classification number: H01L23/49811 ,  H01L23/13 ,  H01L23/16 ,  H01L23/18 ,  H01L23/3157 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13541 ,  H01L2224/13561 ,  H01L2224/13583 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13649 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/1712 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/1751 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

Abstract translation: 半导体封装包括包括中心部分和周边部分的第一基板，附接到第一基板的中心部分的至少一个第一中心连接部件和附接到第一基板的周边部分的至少一个第一周边连接部件。 第一中心连接构件包括第一支撑件和围绕第一支撑件的第一融合导电层。

公开(公告)号：US20120181071A1

公开(公告)日：2012-07-19

申请号：US13431609

申请日：2012-03-27

Applicant: Virendra R. JADHAV ,  Krystyna W. SEMKOW ,  Kamalesh K. SRIVASTAVA ,  Brian R. SUNDLOF

Inventor： Virendra R. JADHAV ,  Krystyna W. SEMKOW ,  Kamalesh K. SRIVASTAVA ,  Brian R. SUNDLOF

IPC: H05K1/09

CPC classification number: H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions

Abstract translation: 提供多层支柱。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其被配置为吸收在芯片组装和热偏移期间施加的力

公开(公告)号：US07462942B2

公开(公告)日：2008-12-09

申请号：US10682054

申请日：2003-10-09

Applicant: Kim Hwee Tan ,  Ch'ng Han Shen ,  Rosemarie Tagapulot ,  Yin Yen Bong ,  Ma L. Nang Htoi ,  Lim Tiong Soon ,  Shikui Lui ,  Balasubramanian Sivagnanam

Inventor： Kim Hwee Tan ,  Ch'ng Han Shen ,  Rosemarie Tagapulot ,  Yin Yen Bong ,  Ma L. Nang Htoi ,  Lim Tiong Soon ,  Shikui Lui ,  Balasubramanian Sivagnanam

IPC: H01L29/40 ,  H01L21/44

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/14051 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A die, comprising a substrate and one or more pillar structures formed over the substrate in a pattern and the method of forming the die.

Abstract translation: 一种模具，其包括基板和以图案形成在所述基板上的一个或多个支柱结构以及形成所述模具的方法。

公开(公告)号：US07348269B2

公开(公告)日：2008-03-25

申请号：US11311800

申请日：2005-12-19

Applicant: Shuichi Tanaka ,  Mitsuru Kuribayashi

Inventor： Shuichi Tanaka ,  Mitsuru Kuribayashi

IPC: H01L21/44

CPC classification number: H01L21/288 ,  G02F1/13452 ,  G02F2001/13456 ,  H01L24/11 ,  H01L24/13 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/136 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/838 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/00014

Abstract: A method for manufacturing a semiconductor device with a bump electrode wherein the bump electrode includes a resin material as a core and at least a top surface covered with a conductive film. The method includes placing the resin material on a substrate on which an electrode terminal is formed by an inkjet method, and forming an interconnecting metal that connects the electrode terminal to a top surface of the resin material.

Abstract translation: 一种用于制造具有凸块电极的半导体器件的方法，其中所述凸块电极包括作为芯的树脂材料和至少覆盖有导电膜的顶表面。 该方法包括通过喷墨方法将树脂材料放置在其上形成有电极端子的基板上，并且形成将电极端子连接到树脂材料的顶表面的互连金属。

公开(公告)号：US06495441B2

公开(公告)日：2002-12-17

申请号：US09533172

申请日：2000-03-22

Applicant: Masayuki Kitajima ,  Masakazu Takesue ,  Yoshitaka Muraoka

Inventor： Masayuki Kitajima ,  Masakazu Takesue ,  Yoshitaka Muraoka

IPC: H01L2144

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K35/26 ,  B23K35/262 ,  B23K35/3013 ,  B23K2101/36 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/0558 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/11822 ,  H01L2224/1184 ,  H01L2224/11901 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1358 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13605 ,  H01L2224/13609 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/742 ,  H01L2224/75 ,  H01L2224/7501 ,  H01L2224/7515 ,  H01L2224/7565 ,  H01L2224/75745 ,  H01L2224/81011 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099

Abstract: A semiconductor device comprises a semiconductor element having electrodes and metal bumps are attached to the electrodes. The metal bumps include copper cores and gold surface layers covering the cores. In addition, the metal bumps may include gold bump elements and solder bump elements connected together.

公开(公告)号：US06333554B1

公开(公告)日：2001-12-25

申请号：US09014981

申请日：1998-01-28

Applicant: Masayuki Kitajima ,  Masakazu Takesue ,  Yoshitaka Muraoka

Inventor： Masayuki Kitajima ,  Masakazu Takesue ,  Yoshitaka Muraoka

IPC: H01L2348

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K35/26 ,  B23K35/262 ,  B23K35/3013 ,  B23K2101/36 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/0558 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/11822 ,  H01L2224/1184 ,  H01L2224/11901 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1358 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13605 ,  H01L2224/13609 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/742 ,  H01L2224/75 ,  H01L2224/7501 ,  H01L2224/7515 ,  H01L2224/7565 ,  H01L2224/75745 ,  H01L2224/81011 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099

Abstract: A semiconductor device comprises a semiconductor element having electrodes and metal bumps are attached to the electrodes. The metal bumps include copper cores and gold surface layers covering the cores. In addition, the metal bumps may include gold bump elements and solder bump elements connected together.

Abstract translation: 半导体器件包括具有电极的半导体元件和附接到电极的金属凸块。 金属凸块包括铜芯和覆盖芯的金表面层。 此外，金属凸块可以包括连接在一起的金突起元件和焊料凸块元件。