公开(公告)号：US11482485B2

公开(公告)日：2022-10-25

申请号：US17073392

申请日：2020-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin

IPC: H01L27/08 ,  H01L23/498 ,  H01L23/00 ,  H01L23/64 ,  H01L23/48 ,  H01L21/48 ,  H01L27/01 ,  H01L21/768

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an interposer substrate having an upper surface and a lower surface that is opposite to the upper surface. A guard ring is formed in the interposer substrate and surrounds a device region of the interposer substrate. At least a through-silicon via is formed in the interposer substrate. An end of the guard ring and an end of the through-silicon via that are near the upper surface of the interposer substrate are flush with each other.

公开(公告)号：US20190221528A1

公开(公告)日：2019-07-18

申请号：US16361880

申请日：2019-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US10323332B2

公开(公告)日：2019-06-18

申请号：US15206321

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ling Lin ,  Yen-Liang Lu ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Chi-Ray Tsai

IPC: C25D7/12 ,  C25D5/00 ,  C25D3/38 ,  C25D5/10 ,  C25D5/54 ,  H01L21/288 ,  H01L21/768

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

公开(公告)号：US20190013259A1

公开(公告)日：2019-01-10

申请号：US15642349

申请日：2017-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chun-Hung Chen ,  Chu-Fu Lin ,  Chun-Ting Yeh ,  Chung-Hsing Kuo ,  Ming-Tse Lin

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor structure includes a substrate having a frontside surface and a backside surface. A through-substrate via extends into the substrate from the frontside surface. The through-substrate via comprises a top surface. A metal cap covers the top surface of the through-substrate via. A plurality of cylindrical dielectric plugs is embedded in the metal cap. The cylindrical dielectric plugs are distributed only within a central area of the metal cap. The central area is not greater than a surface area of the top surface of the through-substrate via.

公开(公告)号：US20160319450A1

公开(公告)日：2016-11-03

申请号：US15206321

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ling Lin ,  Yen-Liang Lu ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Chi-Ray Tsai

IPC: C25D5/54 ,  H01L21/768 ,  C25D7/12 ,  H01L21/288 ,  C25D3/38 ,  C25D5/10

CPC classification number: C25D5/54 ,  C25D3/38 ,  C25D5/00 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76879

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

Abstract translation: 提供电化学镀工艺。 半导体结构设置在电镀平台中。 进行预电镀步骤，其中预电镀步骤在固定电压环境下进行，并且在电流高于电镀平台的阈值电流之后持续0.2至0.5秒。 在预电镀步骤之后，对半导体结构进行第一电镀步骤。

公开(公告)号：US20150179580A1

公开(公告)日：2015-06-25

申请号：US14139879

申请日：2013-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Chun-Hung Chen ,  Yung-Chang Lin ,  Ming-Tse Lin

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating hybrid interconnect structure is disclosed. The method includes the steps of: providing a material layer; forming a through-silicon hole in the material layer; forming a patterned resist on the material layer, wherein the patterned resist comprises at least an opening for exposing the through-silicon hole; and forming a conductive layer to fill the through-silicon hole and the opening in the patterned resist.

Abstract translation: 公开了一种用于制造混合互连结构的方法。 该方法包括以下步骤：提供材料层; 在所述材料层中形成通孔; 在所述材料层上形成图案化的抗蚀剂，其中所述图案化的抗蚀剂至少包括用于暴露所述通孔的孔; 以及形成导电层以填充图案化的抗蚀剂中的通孔和孔。

公开(公告)号：US09024416B2

公开(公告)日：2015-05-05

申请号：US13964184

申请日：2013-08-12

Applicant: United Microelectronics Corp.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin ,  Chien-Li Kuo ,  Kuei-Sheng Wu

IPC: H01L23/552 ,  H01L21/00 ,  H01L23/60 ,  H01L49/02 ,  H01L23/14 ,  H01L23/498 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L23/60 ,  H01L23/147 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/1431 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer.

Abstract translation: 提供半导体结构。 半导体结构包括内插器结构。 插入器结构包括插入器衬底，接地，通孔，电介质层和电感器。 通孔形成在插入器基板中并电连接到地。 介电层位于内插器基板上。 电感在介质层上。

公开(公告)号：US10886241B1

公开(公告)日：2021-01-05

申请号：US17023967

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US10818616B2

公开(公告)日：2020-10-27

申请号：US16361880

申请日：2019-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US20200243386A1

公开(公告)日：2020-07-30

申请号：US16258389

申请日：2019-01-25

Applicant: United Microelectronics Corp.

Inventor： CHU-FU LIN ,  Ming-Tse Lin ,  Chun-Hung Chen

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes providing a preliminary device layer, having a substrate on top and a through substrate via (TSV) structure in the substrate. A top portion of the TSV structure protrudes out from the substrate. A dielectric layer is disposed over the substrate to cover the substrate and the TSV structure. A coating layer is formed over the dielectric layer, wherein the coating layer fully covers over the dielectric layer with a flat surface. An anisotropic etching process is performed to the coating layer and the dielectric layer without etching selection until the TSV structure is exposed.