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    Fin shaped structure and method of forming the same
    21.
    发明授权
    Fin shaped structure and method of forming the same 有权
    翅形结构及其形成方法

    公开(公告)号：US09466691B2

    公开(公告)日：2016-10-11

    申请号：US14541107

    申请日：2014-11-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： I-Ming Tseng ,  Rai-Min Huang ,  Tong-Jyun Huang ,  Kuan-Hsien Li ,  Chen-Ming Huang

    IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/265

    CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

    Abstract: A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure.

    Abstract translation: 鳍状结构及其形成方法，其中，所述方法包括在基板上形成翅片结构。 接下来，在衬底上形成绝缘层并围绕鳍结构，其中绝缘层覆盖翅片结构的底部以暴露从绝缘层突出的鳍结构的暴露部分。 然后，在翅片结构上形成缓冲层。 接下来，在形成绝缘层之后，执行阈值电压注入工艺以穿透缓冲层，以在鳍结构的暴露部分上形成第一掺杂区域。

    FIN SHAPED STRUCTURE AND METHOD OF FORMING THE SAME
    23.
    发明申请
    FIN SHAPED STRUCTURE AND METHOD OF FORMING THE SAME 有权
    FIN形状结构及其形成方法

    公开(公告)号：US20160141387A1

    公开(公告)日：2016-05-19

    申请号：US14541107

    申请日：2014-11-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： I-Ming Tseng ,  Rai-Min Huang ,  Tong-Jyun Huang ,  Kuan-Hsien Li ,  Chen-Ming Huang

    IPC: H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L21/308 ,  H01L29/10 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

    CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

    Abstract: A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure.

    Abstract translation: 鳍状结构及其形成方法，其中，所述方法包括在基板上形成翅片结构。 接下来，在衬底上形成绝缘层并围绕鳍结构，其中绝缘层覆盖翅片结构的底部以暴露从绝缘层突出的鳍结构的暴露部分。 然后，在翅片结构上形成缓冲层。 接下来，在形成绝缘层之后，执行阈值电压注入工艺以穿透缓冲层，以在鳍结构的暴露部分上形成第一掺杂区域。

    FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME
    24.
    发明申请
    FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME 有权
    FINFET晶体管结构及其制造方法

    公开(公告)号：US20140252482A1

    公开(公告)日：2014-09-11

    申请号：US14288369

    申请日：2014-05-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Rai-Min Huang ,  Sheng-Huei Dai ,  Chen-Hua Tsai ,  Duan Quan Liao ,  Yikun Chen ,  Xiao Zhong Zhu

    IPC: H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/0653 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

    Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.

    Abstract translation: FINFET晶体管结构包括包括鳍结构的衬底。 嵌入在基板内的两个组合的凹槽，其中每个组合的凹槽包括沿垂直方向延伸的第一凹部和沿横向方向延伸的第二凹槽，第二凹部具有延伸到翅片结构下方和下方的突出侧。 两个填充层分别填充组合的凹部。 栅极结构穿过鳍结构。

    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
    25.
    发明申请
    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20250040149A1

    公开(公告)日：2025-01-30

    申请号：US18916730

    申请日：2024-10-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

    IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01L23/528 ,  H10N50/80 ,  H10N50/85

    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

    Layout pattern for magnetoresistive random access memory
    26.
    发明授权
    Layout pattern for magnetoresistive random access memory 有权

    公开(公告)号：US12150315B2

    公开(公告)日：2024-11-19

    申请号：US18395649

    申请日：2023-12-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

    IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01L23/528 ,  H10N50/80 ,  H10N50/85

    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    27.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240365677A1

    公开(公告)日：2024-10-31

    申请号：US18329588

    申请日：2023-06-06

    Applicant: United Microelectronics Corp.

    Inventor： Jia-Rong Wu ,  Yi-An Shih ,  Hsiu-Hao Hu ,  I-Fan Chang ,  Rai-Min Huang ,  Po Kai Hsu

    IPC: H10N50/20 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

    CPC classification number: H10N50/20 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80

    Abstract: Provided is a semiconductor device including a substrate, a first interconnection structure, and an MTJ device. The first interconnection structure is disposed on the substrate. The MTJ device is reversely bonded to the first interconnection structure. The MTJ device includes a first electrode layer, a second electrode layer and an MTJ stack structure. The first electrode layer is bonded to the first interconnect structure. The second electrode layer is located above the first electrode layer. The MTJ stack structure is located between the first and second electrode layers. The MTJ stack structure includes a first barrier layer, a free layer and a reference layer. The first barrier layer is located between the first and second electrode layers. The free layer is located between the first barrier layer and the first electrode layer. The reference layer is located between the first barrier layer and the second electrode layer.

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