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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    21.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20150380312A1

    公开(公告)日：2015-12-31

    申请号：US14314425

    申请日：2014-06-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Chi-Mao Hsu ,  Yuan-Chi Pai ,  Yu-Hong Kuo ,  Nien-Ting Ho

    IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/423 ,  H01L21/311

    CPC classification number: H01L21/82385 ,  H01L21/28026 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545

    Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

    Abstract translation: 提供一种制造半导体器件的方法。 该方法包括以下步骤。 形成包括具有第一导电类型的第一晶体管，具有第二导电类型的第二晶体管和具有第一导电类型的第三晶体管的衬底。 内层电介质层形成在衬底上，并且包括对应于第一晶体管的第一栅极沟槽，对应于第二晶体管的第二栅极沟槽和对应于第三晶体管的第三栅极沟槽。 在内层电介质层上形成功函数金属层。 在功函数金属层上涂敷抗反射层。 去除第二晶体管上的抗反射层和第三栅极沟槽的顶部以暴露功函数金属层。 暴露的功能金属层被去除。

    NON-PLANAR TRANSISTOR
    26.
    发明申请
    NON-PLANAR TRANSISTOR 审中-公开

    公开(公告)号：US20170179292A1

    公开(公告)日：2017-06-22

    申请号：US15447134

    申请日：2017-03-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Jhen-Cyuan Li ,  Nan-Yuan Huang ,  Shui-Yen Lu

    IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

    Abstract: A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a first spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The fin structure includes an upper portion, a concave portion and a lower portion, and the concave portion is disposed between the upper portion and the lower portion. The first spacer structure is disposed on a sidewall of the gate structure. The first spacer structure includes a first spacer and a second spacer, wherein the first spacer is disposed between the second spacer, and a height of the first spacer is different from a height of the second spacer. The source/drain region is disposed in a semiconductor layer at two sides of the first spacer structure.

    METHOD OF FORMING RECESS STRUCTURE
    27.
    发明申请
    METHOD OF FORMING RECESS STRUCTURE 审中-公开
    形成结构的方法

    公开(公告)号：US20160163829A1

    公开(公告)日：2016-06-09

    申请号：US14558746

    申请日：2014-12-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuan-Hsuan Ku ,  Jhen-Cyuan Li ,  Shui-Yen Lu

    IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065

    CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/823431 ,  H01L29/7851

    Abstract: The present invention is a method of forming a recess structure. First of all, a substrate is provided, and a first ARC layer is entirely formed on the substrate, covering a first region and a second region thereof. Then, the first ARC layer in the second region is etched with a CH-based gas. Then, a first removing process is performed to form a first recess in the second region. Next, a second ARC layer is entirely formed on the substrate, covering the first region and the second region. Then, the second ARC layer in the first region is etched, also with the CH-based gas, and the CH-based gas includes at least one of CH4, C2H4, C3H6, CHF3, CH2F2, and CH3F. Finally, a second removing process is performed to form a second recess in the first region.

    Abstract translation: 本发明是一种形成凹陷结构的方法。 首先，提供基板，并且第一ARC层完全形成在基板上，覆盖其第一区域和第二区域。 然后，用基于CH的气体蚀刻第二区域中的第一ARC层。 然后，执行第一去除处理以在第二区域中形成第一凹部。 接下来，第二ARC层完全形成在基板上，覆盖第一区域和第二区域。 然后，也蚀刻第一区域中的第二ARC层，并且基于CH的气体，CH基气体包括CH 4，C 2 H 4，C 3 H 6，CHF 3，CH 2 F 2和CH 3 F中的至少一种。 最后，执行第二移除处理以在第一区域中形成第二凹部。

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    28.
    发明申请
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    半导体结构及其制造方法

    公开(公告)号：US20160126334A1

    公开(公告)日：2016-05-05

    申请号：US14562782

    申请日：2014-12-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Jhen-Cyuan Li ,  Shui-Yen Lu ,  Yen-Liang Wu

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L21/31116 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785

    Abstract: The present invention provides a semiconductor structure, including a substrate, having a fin structure disposed thereon, a gate structure, crossing over parts of the fin structure. The top surface of the fin structure which is covered by the gate structure is defined as a first top surface, and the top surface of the fin structure which is not covered by the gate structure is defined as a second top surface. The first top surface is higher than the second top surface, and a spacer covers the sidewalls of the gate structure. The spacer includes an inner spacer and an outer spacer, and the outer pacer further contacts the second top surface of the fin structure directly.

    Abstract translation: 本发明提供一种半导体结构，其包括具有设置在其上的翅片结构的基板，栅极结构，跨越鳍片结构的一部分。 由栅极结构覆盖的翅片结构的上表面被定义为第一顶表面，并且未被栅极结构覆盖的翅片结构的顶表面被定义为第二顶表面。 第一顶表面高于第二顶表面，间隔件覆盖栅结构的侧壁。 间隔件包括内隔离件和外间隔件，并且外起重器还直接接触翅片结构的第二顶表面。

    Method for manufacturing semiconductor device
    29.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09245972B2

    公开(公告)日：2016-01-26

    申请号：US14016393

    申请日：2013-09-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Yuan-Chi Pai ,  Fong-Lung Chuang

    IPC: H01L29/66 ,  H01L21/8234

    CPC classification number: H01L29/66484 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

    Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.

    Abstract translation: 提供一种制造半导体器件的方法。 提供分别形成在第一区域和第二区域中的具有第一栅极和第二栅极的衬底。 在衬底上形成底层以覆盖第一区域中的第一栅极和第二区域中的第二栅极。 在第一区域中的底层上形成具有预定厚度的图案化掩模。 通过图案化掩模去除对应于第二区域中的第二栅极的底层以暴露第二栅极，其中对应于第一区域中的第一栅极的底层被部分消耗以暴露第一栅极的部分。

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