公开(公告)号：US20170263732A1

公开(公告)日：2017-09-14

申请号：US15481419

申请日：2017-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Yi-Fan Li ,  Kun-Hsin Chen ,  Tong-Jyun Huang ,  Jyh-Shyang Jenq ,  Nan-Yuan Huang

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26546 ,  H01L29/1054 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes dopants selected from the group consisting of P, As, Sb, Bi, C, and F.

公开(公告)号：US09680022B1

公开(公告)日：2017-06-13

申请号：US15207916

申请日：2016-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Yen-Hsing Chen ,  Chun-Yu Chen ,  Chung-Ting Huang ,  Zih-Hsuan Huang ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

公开(公告)号：US12237394B2

公开(公告)日：2025-02-25

申请号：US18226262

申请日：2023-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US20240332087A1

公开(公告)日：2024-10-03

申请号：US18739286

申请日：2024-06-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US20240274715A1

公开(公告)日：2024-08-15

申请号：US18123995

申请日：2023-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Hsiang Wang ,  Yi-Fan Li ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Chun-Jen Chen ,  Ti-Bin Chen ,  Chih-Chiang Wu

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66636

Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, an anisotropic layer on the first buffer layer, a second buffer layer on the first buffer layer, and a bulk layer on the anisotropic layer. Preferably, a concentration of boron in the bulk layer is less than a concentration of boron in the anisotropic layer, a concentration of boron in the first buffer layer is less than a concentration of boron in the second buffer layer, and the concentration of boron in the second buffer layer is less than the concentration of boron in the anisotropic layer.

公开(公告)号：US20230369442A1

公开(公告)日：2023-11-16

申请号：US18226264

申请日：2023-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih- Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L27/092 ,  H01L29/401

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US20230369441A1

公开(公告)日：2023-11-16

申请号：US18226262

申请日：2023-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/40

CPC classification number: H01L29/4966 ,  H01L27/092 ,  H01L29/401

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US11705492B2

公开(公告)日：2023-07-18

申请号：US17246726

申请日：2021-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/41775 ,  H01L21/31116 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/7843 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

Abstract: A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.

公开(公告)号：US20230005795A1

公开(公告)日：2023-01-05

申请号：US17393387

申请日：2021-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/423

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US10541309B2

公开(公告)日：2020-01-21

申请号：US15853867

申请日：2017-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes first and second metal gates on a substrate with a gap therebetween. The first metal gate has a first sidewall, and the second metal gate has a second sidewall directly facing the first sidewall. A contact etch stop layer (CESL) is disposed within the gap and extends along the first and second sidewalls. The CESL has a first top portion adjacent to a top surface of the first metal gate and a second top portion adjacent to a top surface of the second metal gate. The first top portion and the second top portion have a trapezoid cross-sectional profile. A first sidewall spacer is disposed on the first sidewall and between the CESL and the first metal gate. A second sidewall spacer is disposed on the second sidewall and between the CESL and the second metal gate.