-
21.
公开(公告)号:US20170110192A1
公开(公告)日:2017-04-20
申请号:US15382755
申请日:2016-12-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: ZHIBIAO ZHOU , Chen-Bin Lin , Chi-Fa Ku , Shao-Hui Wu
IPC: G11C14/00 , H01L49/02 , H01L29/04 , H01L27/105 , H01L29/24 , H01L29/66 , H01L27/108
CPC classification number: G11C14/0009 , G11C14/0027 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02194 , H01L27/10808 , H01L27/1085 , H01L27/1225 , H01L27/1255 , H01L27/1259 , H01L28/60
Abstract: A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.
-
公开(公告)号:US20170098599A1
公开(公告)日:2017-04-06
申请号:US14873189
申请日:2015-10-01
Applicant: United Microelectronics Corp.
Inventor: ZHIBIAO ZHOU , Shao-Hui Wu , Chi-Fa Ku , Chen-Bin Lin
IPC: H01L23/498 , H01L27/108 , H01L27/115 , H01L29/66 , H01L27/12 , H01L21/48 , H01L29/786
CPC classification number: H01L23/49827 , H01L21/486 , H01L23/147 , H01L23/49816 , H01L23/49822 , H01L23/5223 , H01L23/5385 , H01L27/1218 , H01L27/1225 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/1259 , H01L27/1262 , H01L29/66969 , H01L29/7869 , H01L2224/16225 , H01L2924/15311
Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. An interposer substrate is provided. At least one oxide semiconductor transistor is formed on the interposer substrate. At least one trough silicon via (TSV) is formed in the interposer substrate. An interconnection structure on the interposer substrate, and the at least one oxide semiconductor transistor is connected to the interconnection structure.
-
公开(公告)号:US20160322502A1
公开(公告)日:2016-11-03
申请号:US14724799
申请日:2015-05-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: ZHIBIAO ZHOU , Shao-Hui Wu , Chi-Fa Ku
IPC: H01L29/786 , H01L29/51 , H01L29/49 , H01L29/24 , H01L29/04
CPC classification number: H01L29/7869 , H01L27/1218 , H01L27/1225 , H01L29/045 , H01L29/0649 , H01L29/24 , H01L29/4908 , H01L29/4916 , H01L29/517 , H01L29/66969 , H01L29/78603
Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.
Abstract translation: 半导体结构包括基板和设置在基板中并沿着第一方向布置的第一元件。 第一元件由半导体氧化物材料制成。 半导体结构还包括设置在第一元件上的电介质层和设置在电介质层上并沿着第一方向布置的第二元件。 第二个元件用作晶体管结构的栅极。
-
公开(公告)号:US20160163693A1
公开(公告)日:2016-06-09
申请号:US14588991
申请日:2015-01-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: ZHIBIAO ZHOU , Shao-Hui Wu , Chi-Fa Ku
Abstract: A structure with an inductor and a MIM capacitor is provided. The structure includes a dielectric layer, an inductor and a MIM capacitor. The inductor and the MIM capacitor are disposed within the dielectric layer. The inductor includes a core and a wire surrounding the core. The MIM capacitor includes a top electrode, a bottom electrode and an insulating layer. The top electrode or the bottom electrode includes a material which forms the core.
Abstract translation: 提供具有电感器和MIM电容器的结构。 该结构包括电介质层,电感器和MIM电容器。 电感器和MIM电容器设置在电介质层内。 电感器包括芯和围绕芯的导线。 MIM电容器包括顶电极,底电极和绝缘层。 顶部电极或底部电极包括形成芯的材料。
-
公开(公告)号:US20250006723A1
公开(公告)日:2025-01-02
申请号:US18225706
申请日:2023-07-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: ZHIBIAO ZHOU
Abstract: A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a substrate, a pickup region adjacent to one side of the first MOS transistor, and a protection diode adjacent to another side of the first MOS transistor. Preferably, the first MOS transistor includes a first gate structure on the substrate and a first source/drain region adjacent to two sides of the first gate structure, the protection diode is electrically connected to the first gate structure, and the pickup region and the protection diode include different conductive type.
-
公开(公告)号:US20230335629A1
公开(公告)日:2023-10-19
申请号:US17746923
申请日:2022-05-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: ZHIBIAO ZHOU
IPC: H01L29/778 , H01L29/45 , H01L29/47
CPC classification number: H01L29/778 , H01L29/45 , H01L29/47
Abstract: A high electron mobility transistor (HEMT) includes a first doped layer disposed in a substrate, a mesa isolation disposed on the substrate, a gate electrode disposed on the mesa isolation, a source electrode and a drain electrode disposed adjacent to two sides of the gate electrode, a passivation layer disposed on the mesa isolation and around the source electrode and the drain electrode, a first metal line connecting the source electrode and the first doped layer, and a second metal line connecting the drain electrode and the first doped layer.
-
公开(公告)号:US20230082878A1
公开(公告)日:2023-03-16
申请号:US17502026
申请日:2021-10-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: BO TAO , Li Wang , Ching-Yang Wen , Purakh Raj Verma , ZHIBIAO ZHOU , DONG YIN , Gang Ren , Jian Xie
IPC: H01L27/12 , H01L23/525 , H01L27/112 , G11C17/16
Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.
-
28.
公开(公告)号:US20220373801A1
公开(公告)日:2022-11-24
申请号:US17355196
申请日:2021-06-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: ZHIBIAO ZHOU
IPC: G02B27/01 , H01L25/075 , H01L33/62
Abstract: A layout of Micro LED for augmented reality (AR) and mixed reality (MR) is provided in the present invention, including multiple display cells arranging into a cell array, multiple micro LEDs set on the edge region of each display cell and exposing the transparent region surrounded by the edge region, and pixel driver circuits set on the edge region right under the Micro LEDs.
-
公开(公告)号:US20200294933A1
公开(公告)日:2020-09-17
申请号:US16371077
申请日:2019-03-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: ZHIBIAO ZHOU
IPC: H01L23/552 , H01L27/06 , H01L27/12 , H01L21/84 , H01L21/822 , H01L27/02 , H01L23/528 , H01L23/66
Abstract: A semiconductor structure is provided, the semiconductor structure includes a front oxide layer on a backside oxide layer, a front electronic component in the front oxide layer, a backside electronic component in the backside oxide layer, and a shield structure disposed between the front oxide layer and the backside oxide layer, the shield structure includes a patterned buried metal layer, two front contact structures disposed on a front surface of the patterned buried metal layer, and two back contact structures disposed on a backside of the patterned buried metal layer.
-
公开(公告)号:US20190027607A1
公开(公告)日:2019-01-24
申请号:US16131014
申请日:2018-09-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: ZHIBIAO ZHOU , Shao-Hui Wu , Chi-Fa Ku
Abstract: The present invention provides a method for forming a semiconductor structure, the method includes: firstly, a substrate having a recess disposed therein is provided, wherein the substrate comprises a silicon substrate, next, a first element is formed in the recess and arranged along a first direction, wherein the first element is made of an oxidation semiconductor material, afterwards, a dielectric layer is formed on the first element, and a second element is formed on dielectric layer and arranged along the first direction, wherein the second element is used as the gate structure of a transistor structure.
-
-
-
-
-
-
-
-
-