公开(公告)号：US20110291171A1

公开(公告)日：2011-12-01

申请号：US13050043

申请日：2011-03-17

申请人： John J. Pekarik ,  William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Yun Shi ,  Yanli Zhang

发明人： John J. Pekarik ,  William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Yun Shi ,  Yanli Zhang

IPC分类号： H01L29/92 ,  H01L21/8234

CPC分类号： H01L29/93 ,  H01L27/0808 ,  H01L27/0811 ,  H01L29/78

摘要： A variable capacitance device including a plurality of FETs, the sources and drains of each FET being coupled to a first terminal, the gates of each FET being coupled to a second terminal, the capacitance of said device between said first and second terminals varying as a function of the voltage across said terminals, the device further including a biasing providing a respective backgate bias voltage to each the FETs setting a respective gate threshold voltage thereof. The aggregate V-C characteristic can be tuned as desired, either at design time or dynamically. The greater the number of FETs forming the varactor, the greater the number of possible Vt values that can be individually set, so that arbitrary V-C characteristics can be more closely approximated.

摘要翻译： 一种包括多个FET的可变电容器件，每个FET的源极和漏极耦合到第一端子，每个FET的栅极耦合到第二端子，所述器件在所述第一和第二端子之间的电容变化为 所述器件还包括偏置电路，为每个FET提供相应的背栅极偏置电压，从而设置其相应的栅极阈值电压。 可以在设计时或动态地根据需要调整总体V-C特性。 形成变容二极管的FET数量越多，可以单独设置的可能的Vt值的数量就越多，从而可以更接近任意的V-C特性。

公开(公告)号：US08598660B2

公开(公告)日：2013-12-03

申请号：US13150612

申请日：2011-06-01

申请人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, Jr. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

发明人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, Jr. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66492 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7843

摘要： A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

公开(公告)号：US20120326766A1

公开(公告)日：2012-12-27

申请号：US13168232

申请日：2011-06-24

申请人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Yun Shi ,  Andreas D. Stricker

发明人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Yun Shi ,  Andreas D. Stricker

IPC分类号： H03K17/72 ,  H01L29/74 ,  G06F17/50 ,  H01L21/311

CPC分类号： H01L29/7315 ,  G06F17/5063 ,  H01L27/0262 ,  H01L29/66393 ,  H01L29/7436

摘要： Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

摘要翻译： 可控硅整流器的器件结构，制造方法，操作方法和设计结构。 该方法包括以足以调节SCR的触发电流的水平对可控硅整流器（SCR）的区域施加机械应力。 装置和设计结构包括具有阳极的SCR，阴极，第一区域和与第一区域相反的导电类型的第二区域。 SCR的第一和第二区域设置在SCR的阳极和阴极之间的通电路径中。 层相对于第一区域定位在半导体衬底的顶表面上，并且被配置为在SCR的第一区域中产生一个足以调制SCR的触发电流的电平的机械应力。

公开(公告)号：US20120306014A1

公开(公告)日：2012-12-06

申请号：US13150612

申请日：2011-06-01

申请人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

发明人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66492 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7843

摘要： A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

摘要翻译： 横向扩散金属氧化物半导体场效应晶体管（LDMOS晶体管）采用增强载流子迁移率（即导通电流）的应力层，同时还保持器件的高击穿电压。 由于漂移区域的掺杂浓度的增加被最小化，因此保持高的击穿电压。 在相邻的衬底中形成阱区和漂移区。 第一浅沟槽隔离（STI）区域形成在阱区域上并与阱区域相邻，并且第二STI区域形成在漂移区域上并与漂移区域相邻。 应力层沉积在LDMOS晶体管和第二STI区域中，第二STI区域根据应力层的极性将压缩或拉伸应力传播到漂移区域。 应力层的一部分可以在栅极上去除以改变栅极下方的反转区域中的应力极性。

公开(公告)号：US09041105B2

公开(公告)日：2015-05-26

申请号：US13553947

申请日：2012-07-20

申请人： William F. Clark, Jr. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

发明人： William F. Clark, Jr. ,  Qizhi Liu ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L21/265

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.

摘要翻译： 一种集成电路（IC）及其制造方法。 在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。

公开(公告)号：US08921190B2

公开(公告)日：2014-12-30

申请号：US12099175

申请日：2008-04-08

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7834 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/423 ,  H01L29/66575

摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

摘要翻译： 提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。 该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。 有源区具有不同于第一导电类型的第二导电类型。 接触区域与有源区域电接触。 该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。

公开(公告)号：US08618583B2

公开(公告)日：2013-12-31

申请号：US13108305

申请日：2011-05-16

申请人： Panglijen Candra ,  Richard A. Phelps ,  Robert M. Rassel ,  Yun Shi

发明人： Panglijen Candra ,  Richard A. Phelps ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L29/66 ,  H01L21/70 ,  H01L21/337

CPC分类号： H01L29/808 ,  H01L29/0649 ,  H01L29/1075 ,  H01L29/66901

摘要： The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.

摘要翻译： 本公开总体上涉及结栅场效应晶体管（JFET）结构及其形成方法。 JFET结构包括其中具有p区的p型衬底; 一条n通道; 在n沟道内的n掺杂的增强区域，每个n掺杂的增强区域与p区域分离。

公开(公告)号：US20100248432A1

公开(公告)日：2010-09-30

申请号：US12795108

申请日：2010-06-07

申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L21/84 ,  G06F17/50

CPC分类号： H01L29/93

摘要： Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.

摘要翻译： 形成超突变p-n结的方法和包含具有超突变p-n结的器件结构的集成电路的设计结构。 通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。 反渗透定义了超突变p-n结。 在离子注入期间，在器件层的顶表面上承载的栅结构作为硬掩模进行操作，以有助于限定超突变p-n结的横向边界。

公开(公告)号：US07804119B2

公开(公告)日：2010-09-28

申请号：US12099316

申请日：2008-04-08

申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L27/108

CPC分类号： H01L29/93

摘要： Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.

摘要翻译： 具有超突变p-n结的器件结构，形成超突变p-n结的方法以及包含具有超突变p-n结的器件结构的集成电路的设计结构。 通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。 反渗透定义了超突变p-n结。 在离子注入期间，在器件层的顶表面上承载的栅极结构作为硬掩模进行操作，以有助于限定超突变n结的横向边界。

公开(公告)号：US20130134518A1

公开(公告)日：2013-05-30

申请号：US13280681

申请日：2011-11-28

申请人： Alan B. Botula ,  William F. Clark, JR. ,  Richard A. Phelps ,  BethAnn Rainey ,  Yun Shi ,  James A. Slinkman

发明人： Alan B. Botula ,  William F. Clark, JR. ,  Richard A. Phelps ,  BethAnn Rainey ,  Yun Shi ,  James A. Slinkman

IPC分类号： H01L27/088 ,  H01L21/302

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.

摘要翻译： 半导体结构包括绝缘体上半导体衬底，绝缘体上半导体衬底包括处理晶片，处理晶片顶部的掩埋氧化物（BOX）层和位于BOX层顶部的顶部硅层; 以及位于顶部硅层中的注入区域，该注入区域包括惰性气体。