公开(公告)号：US08598660B2

公开(公告)日：2013-12-03

申请号：US13150612

申请日：2011-06-01

申请人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, Jr. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

发明人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, Jr. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66492 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7843

摘要： A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

公开(公告)号：US20120306014A1

公开(公告)日：2012-12-06

申请号：US13150612

申请日：2011-06-01

申请人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

发明人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66492 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7843

摘要： A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

摘要翻译： 横向扩散金属氧化物半导体场效应晶体管（LDMOS晶体管）采用增强载流子迁移率（即导通电流）的应力层，同时还保持器件的高击穿电压。 由于漂移区域的掺杂浓度的增加被最小化，因此保持高的击穿电压。 在相邻的衬底中形成阱区和漂移区。 第一浅沟槽隔离（STI）区域形成在阱区域上并与阱区域相邻，并且第二STI区域形成在漂移区域上并与漂移区域相邻。 应力层沉积在LDMOS晶体管和第二STI区域中，第二STI区域根据应力层的极性将压缩或拉伸应力传播到漂移区域。 应力层的一部分可以在栅极上去除以改变栅极下方的反转区域中的应力极性。

公开(公告)号：US08586423B2

公开(公告)日：2013-11-19

申请号：US13168232

申请日：2011-06-24

申请人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Robert J. Gauthier, Jr. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Yun Shi ,  Andreas Stricker

发明人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Robert J. Gauthier, Jr. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Yun Shi ,  Andreas Stricker

IPC分类号： H01L21/02

CPC分类号： H01L29/7315 ,  G06F17/5063 ,  H01L27/0262 ,  H01L29/66393 ,  H01L29/7436

摘要： Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

公开(公告)号：US20120326766A1

公开(公告)日：2012-12-27

申请号：US13168232

申请日：2011-06-24

申请人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Yun Shi ,  Andreas D. Stricker

发明人： Renata Camillo-Castillo ,  Erik M. Dahlstrom ,  Robert J. Gauthier, JR. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Yun Shi ,  Andreas D. Stricker

IPC分类号： H03K17/72 ,  H01L29/74 ,  G06F17/50 ,  H01L21/311

CPC分类号： H01L29/7315 ,  G06F17/5063 ,  H01L27/0262 ,  H01L29/66393 ,  H01L29/7436

摘要： Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.

摘要翻译： 可控硅整流器的器件结构，制造方法，操作方法和设计结构。 该方法包括以足以调节SCR的触发电流的水平对可控硅整流器（SCR）的区域施加机械应力。 装置和设计结构包括具有阳极的SCR，阴极，第一区域和与第一区域相反的导电类型的第二区域。 SCR的第一和第二区域设置在SCR的阳极和阴极之间的通电路径中。 层相对于第一区域定位在半导体衬底的顶表面上，并且被配置为在SCR的第一区域中产生一个足以调制SCR的触发电流的电平的机械应力。

公开(公告)号：US07791105B2

公开(公告)日：2010-09-07

申请号：US12121286

申请日：2008-05-15

申请人： Renata Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Andreas D. Stricker

发明人： Renata Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Andreas D. Stricker

IPC分类号： H01L29/778

CPC分类号： H01L29/808 ,  H01L29/0692

摘要： Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer.

摘要翻译： 高压结场效应晶体管的器件结构和高压集成电路的设计结构。 使用具有第一晶体取向的第一半导体层，具有第二晶体取向的第二半导体层和在第一和第二半导体层之间的绝缘层的混合定向技术晶片制造器件结构。 器件结构包括具有第二晶体取向的外延半导体区域和外延半导体区域中的第一和第二p-n结。 外延半导体区域从第二半导体层延伸穿过绝缘层和第一半导体层朝向第一半导体层的顶表面延伸。 第一和第二p-n结在第二半导体层和第一半导体层的顶表面之间的外延半导体区域内被深入布置。

公开(公告)号：US20090258464A1

公开(公告)日：2009-10-15

申请号：US12099904

申请日：2008-04-09

申请人： Renata Camillo-Castillo ,  Robert J. Gauthier, JR. ,  Richard A. Phelps ,  Andreas D. Stricker

发明人： Renata Camillo-Castillo ,  Robert J. Gauthier, JR. ,  Richard A. Phelps ,  Andreas D. Stricker

IPC分类号： H01L21/337

CPC分类号： H01L29/808 ,  H01L27/098 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/66901

摘要： Methods for manufacturing a high voltage junction field effect transistor. The method includes forming an opening extending from a top surface of a device layer of a hybrid orientation technology (HOT) wafer through the device layer and an insulating layer to expose a portion of a bulk layer, and filling the opening with epitaxial semiconductor material having the crystalline orientation of the bulk layer. The method further includes forming first and second p-n junctions in the epitaxial semiconductor material that are arranged in depth within the epitaxial semiconductor material between the second semiconductor layer and the top surface of the first semiconductor layer.

摘要翻译： 制造高压结场效应晶体管的方法。 该方法包括从混合定向技术（HOT）晶片的器件层的顶表面延伸通过器件层和绝缘层形成开口以露出本体层的一部分，并且用具有外延半导体材料的开口填充开口，该外延半导体材料具有 本体层的晶体取向。 该方法还包括在外延半导体材料中形成在第二半导体层和第一半导体层的顶表面之间的外延半导体材料内的深度布置的第一和第二p-n结。

公开(公告)号：US20090256174A1

公开(公告)日：2009-10-15

申请号：US12121286

申请日：2008-05-15

申请人： Renata Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Andreas D. Stricker

发明人： Renata Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Andreas D. Stricker

IPC分类号： H01L29/778

CPC分类号： H01L29/808 ,  H01L29/0692

摘要： Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer.

摘要翻译： 高压结场效应晶体管的器件结构和高压集成电路的设计结构。 使用具有第一晶体取向的第一半导体层，具有第二晶体取向的第二半导体层和在第一和第二半导体层之间的绝缘层的混合定向技术晶片制造器件结构。 器件结构包括具有第二晶体取向的外延半导体区域和外延半导体区域中的第一和第二p-n结。 外延半导体区域从第二半导体层延伸穿过绝缘层和第一半导体层朝向第一半导体层的顶表面延伸。 第一和第二p-n结在第二半导体层和第一半导体层的顶表面之间的外延半导体区域内被深入布置。

公开(公告)号：US20110156223A1

公开(公告)日：2011-06-30

申请号：US12647796

申请日：2009-12-28

申请人： Renata A. Camillo-Castillo ,  Robert J. Gauthier, JR. ,  Richard A. Phelps ,  Robert M. Rassel ,  Andreas D. Stricker

发明人： Renata A. Camillo-Castillo ,  Robert J. Gauthier, JR. ,  Richard A. Phelps ,  Robert M. Rassel ,  Andreas D. Stricker

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L29/8086 ,  H01L21/76283 ,  H01L29/66901 ,  H01L29/7846

摘要： An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed.

摘要翻译： 提供了一种集成电路（IC）芯片，其包括至少一个沟槽，该至少一个沟槽包括在器件的沟道区域上施加应力的应力诱导材料，诸如结栅场效应晶体管（JFET）或金属氧化物 - 半导体场效应晶体管（MOSFET）。 还公开了相关方法。

公开(公告)号：US08242584B2

公开(公告)日：2012-08-14

申请号：US12647796

申请日：2009-12-28

申请人： Renata A. Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Robert M. Rassel ,  Andreas D. Stricker

发明人： Renata A. Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Robert M. Rassel ,  Andreas D. Stricker

IPC分类号： H01L29/06

CPC分类号： H01L29/8086 ,  H01L21/76283 ,  H01L29/66901 ,  H01L29/7846

摘要： An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed.

摘要翻译： 提供了一种集成电路（IC）芯片，其包括至少一个沟槽，该至少一个沟槽包括在器件的沟道区域上施加应力的应力诱导材料，诸如结栅场效应晶体管（JFET）或金属氧化物 - 半导体场效应晶体管（MOSFET）。 还公开了相关方法。

公开(公告)号：US20130134518A1

公开(公告)日：2013-05-30

申请号：US13280681

申请日：2011-11-28

申请人： Alan B. Botula ,  William F. Clark, JR. ,  Richard A. Phelps ,  BethAnn Rainey ,  Yun Shi ,  James A. Slinkman

发明人： Alan B. Botula ,  William F. Clark, JR. ,  Richard A. Phelps ,  BethAnn Rainey ,  Yun Shi ,  James A. Slinkman

IPC分类号： H01L27/088 ,  H01L21/302

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.

摘要翻译： 半导体结构包括绝缘体上半导体衬底，绝缘体上半导体衬底包括处理晶片，处理晶片顶部的掩埋氧化物（BOX）层和位于BOX层顶部的顶部硅层; 以及位于顶部硅层中的注入区域，该注入区域包括惰性气体。