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1.发明授权Backside integration of RF filters for RF front end modules and design structure 有权用于RF前端模块的RF滤波器的背面集成和设计结构公开(公告)号：US09058455B2
公开(公告)日：2015-06-16
申请号：US13354705
申请日：2012-01-20
Applicant: James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
Inventor： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC: G06F17/50 , H01L21/768 , H01L23/48 , H03H9/64 , H01L23/00 , H01L27/06 , H01L49/02 , H01L23/66 , H01L25/16
CPC classification number: H01L41/293 , G06F17/5063 , G06F17/5068 , H01L21/76898 , H01L23/481 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/24 , H01L25/16 , H01L27/0694 , H01L28/40 , H01L41/0815 , H01L41/25 , H01L2224/03009 , H01L2224/0401 , H01L2224/04105 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/12105 , H01L2224/14181 , H01L2224/16145 , H01L2224/24145 , H01L2225/06548 , H03H9/64
Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.
Abstract translation: 在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。
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公开(公告)号：US08723392B2
公开(公告)日：2014-05-13
申请号：US13183977
申请日：2011-07-15
Applicant: James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
Inventor： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
IPC: H03H9/25
CPC classification number: H03H9/14538 , H03H3/08
Abstract: Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate; a planar barrier layer disposed above the piezoelectric substrate, and at least one conductor buried in the piezoelectric substrate and the planar barrier layer.
Abstract translation: 本文公开了一种表面声波（SAW）滤波器及其制造方法。 SAW滤波器包括压电基片; 设置在所述压电基板上方的平面阻挡层，以及埋设在所述压电基板和所述平面阻挡层中的至少一个导体。
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公开(公告)号：US20120292669A1
公开(公告)日：2012-11-22
申请号：US13108305
申请日：2011-05-16
Applicant: Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
Inventor： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC: H01L29/772 , H01L21/336
CPC classification number: H01L29/808 , H01L29/0649 , H01L29/1075 , H01L29/66901
Abstract: The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.
Abstract translation: 本公开总体上涉及结栅场效应晶体管（JFET）结构及其形成方法。 JFET结构包括其中具有p区的p型衬底; 一条n通道; 在n沟道内的n掺杂的增强区域，每个n掺杂的增强区域与p区域分离。
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公开(公告)号：US08168474B1
公开(公告)日：2012-05-01
申请号：US12987402
申请日：2011-01-10
Applicant: James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Yen L. Lim
Inventor： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Yen L. Lim
IPC: H01L21/00
CPC classification number: H01L21/78 , H01L21/76898
Abstract: Systems and methods simultaneously form first openings and second openings in a substrate. The first openings are formed smaller than the second openings. The method also simultaneously forms a first material in the first openings and the second openings. The first material fills the first openings, and the first material lines the second openings. The method forms a second material different than the first material in the second openings. The second material fills the second openings. The method forms a plurality of integrated circuit structures over the first material and the second material within the second openings. The method applies mechanical stress to the substrate to cause the substrate to split along the first openings.
Abstract translation: 系统和方法同时在衬底中形成第一开口和第二开口。 第一开口形成为小于第二开口。 该方法还同时在第一开口和第二开口中形成第一材料。 第一材料填充第一开口，第一材料将第二开口排列。 该方法形成与第二开口中的第一材料不同的第二材料。 第二材料填充第二开口。 该方法在第二开口内的第一材料和第二材料上形成多个集成电路结构。 该方法对基板施加机械应力以使基板沿着第一开口分开。
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公开(公告)号：US09252204B2
公开(公告)日：2016-02-02
申请号：US13233752
申请日：2011-09-15
Applicant: James W. Adkisson , Panglijen Candra , Kevin N. Ogg , Anthony K. Stamper
Inventor： James W. Adkisson , Panglijen Candra , Kevin N. Ogg , Anthony K. Stamper
IPC: H01L49/02
CPC classification number: H01L28/90
Abstract: A MIM capacitor includes a dielectric cap that enhances performance and reduces damage to MIM insulators during manufacture. A cavity is formed in an insulative substrate, such as a back end of line dielectric layer, and a first metal layer and an insulator layer are conformally deposited. A second metal layer may be deposited conformally and/or to fill a remaining portion of the cavity. The dielectric cap may be an extra layer of insulative material deposited at ends of the insulator at an opening of the cavity and may also be formed as part of the insulator layer.
Abstract translation: MIM电容器包括在制造期间增强性能并减少对MIM绝缘体的损坏的电介质盖。 在绝缘基板（例如线路介质层的后端）中形成空腔，并且第一金属层和绝缘体层被共形沉积。 可以共形地沉积第二金属层和/或填充空腔的剩余部分。 电介质盖可以是在空腔的开口处沉积在绝缘体的端部处的绝缘材料的额外层，并且还可以形成为绝缘体层的一部分。
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Patent Agency Ranking
公开(公告)号：US09099982B2
公开(公告)日：2015-08-04
申请号：US13358172
申请日：2012-01-25
Applicant: James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
Inventor： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
CPC classification number: H03H9/13 , G06F17/5081 , H01L41/08 , H03H3/08 , H03H9/02543 , H03H9/64 , H03H9/6403 , H03H9/6413 , H03H2003/0071 , H03H2009/02299 , Y10T29/42 , Y10T29/49005 , Y10T29/49126 , Y10T29/49147 , Y10T29/49155
Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are provided herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a fixed electrode with a plurality of fingers on the piezoelectric substrate. The method further includes forming a moveable electrode with a plurality of fingers over the piezoelectric substrate. The method further includes forming actuators aligned with one or more of the plurality of fingers of the moveable electrode.
Abstract translation: 本发明提供了可切换和/或可调滤波器，制造方法和设计结构。 形成滤波器的方法包括形成至少一个包括形成在压电基片上的多个电极的压电滤波器结构。 该方法还包括在压电基片上形成多个指状物的固定电极。 该方法还包括在压电衬底上形成具有多个指状物的可移动电极。 该方法还包括形成与可移动电极的多个指状物中的一个或多个对准的致动器。
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公开(公告)号：US09054671B2
公开(公告)日：2015-06-09
申请号：US13292729
申请日：2011-11-09
Applicant: James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Mark D. Jaffe , Robert K. Leidy , Anthony K. Stamper
Inventor： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Mark D. Jaffe , Robert K. Leidy , Anthony K. Stamper
CPC classification number: H03H9/545 , H03H9/0547 , H03H9/171 , H03H9/173 , H03H9/56 , H03H2009/02204 , Y10T29/42
Abstract: Tunable filter structures, methods of manufacture and design structures are disclosed. The method of forming a filter structure includes forming a piezoelectric resonance filter over a cavity structure. The forming of the piezoelectric resonance filter includes: forming an upper electrode on one side of a piezoelectric material; and forming a lower electrode on an opposing side of the piezoelectric material. The method further includes forming a micro-electro-mechanical structure (MEMS) cantilever beam at a location in which, upon actuation, makes contact with the piezoelectric resonance filter.
Abstract translation: 公开了可调谐滤波器结构，制造方法和设计结构。 形成滤波器结构的方法包括在空腔结构上形成压电谐振滤波器。 压电谐振滤波器的形成包括：在压电材料的一侧上形成上电极; 以及在所述压电材料的相对侧上形成下电极。 该方法还包括在致动时与压电谐振滤波器接触的位置处形成微机电结构（MEMS）悬臂梁。
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公开(公告)号：US20130069199A1
公开(公告)日：2013-03-21
申请号：US13233752
申请日：2011-09-15
Applicant: James W. Adkisson , Panglijen Candra , Kevin N. Ogg , Anthony K. Stamper
Inventor： James W. Adkisson , Panglijen Candra , Kevin N. Ogg , Anthony K. Stamper
CPC classification number: H01L28/90
Abstract: A MIM capacitor includes a dielectric cap that enhances performance and reduces damage to MIM insulators during manufacture. A cavity is formed in an insulative substrate, such as a back end of line dielectric layer, and a first metal layer and an insulator layer are conformally deposited. A second metal layer may be deposited conformally and/or to fill a remaining portion of the cavity. The dielectric cap may be an extra layer of insulative material deposited at ends of the insulator at an opening of the cavity and may also be formed as part of the insulator layer.
Abstract translation: MIM电容器包括在制造期间增强性能并减少对MIM绝缘体的损坏的电介质盖。 在绝缘基板（例如线路介质层的后端）中形成空腔，并且第一金属层和绝缘体层被共形沉积。 可以共形地沉积第二金属层和/或填充空腔的剩余部分。 电介质盖可以是在空腔的开口处沉积在绝缘体的端部处的绝缘材料的额外层，并且还可以形成为绝缘体层的一部分。
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9.发明授权Method of manufacturing a film bulk acoustic resonator with a loading element 有权制造具有加载元件的薄膜体声波谐振器的方法公开(公告)号：US08910355B2
公开(公告)日：2014-12-16
申请号：US13323285
申请日：2011-12-12
Applicant: James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
Inventor： James W. Adkisson , Panglijen Candra , Thomas J. Dunbar , Jeffrey P. Gambino , Mark D. Jaffe , Anthony K. Stamper , Randy L. Wolf
CPC classification number: H03H3/04 , C23C16/401 , C23C16/402 , H03H3/007 , H03H3/02 , H03H9/1007 , H03H9/105 , H03H9/1085 , H03H9/1092 , H03H9/173 , H03H2003/021 , H03H2003/0428 , Y10T29/42 , Y10T29/49005 , Y10T29/49126 , Y10T29/49155
Abstract: Manufacturing a semiconductor structure including modifying a frequency of a Film Bulk Acoustic Resonator (FBAR) device though a vent hole of a sealing layer surrounding the FBAR device.
Abstract translation: 制造半导体结构，包括通过围绕FBAR器件的密封层的通气孔来修改膜体声波谐振器（FBAR）器件的频率。
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公开(公告)号：US08618583B2
公开(公告)日：2013-12-31
申请号：US13108305
申请日：2011-05-16
Applicant: Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
Inventor： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC: H01L29/66 , H01L21/70 , H01L21/337
CPC classification number: H01L29/808 , H01L29/0649 , H01L29/1075 , H01L29/66901
Abstract: The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.
Abstract translation: 本公开总体上涉及结栅场效应晶体管（JFET）结构及其形成方法。 JFET结构包括其中具有p区的p型衬底; 一条n通道; 在n沟道内的n掺杂的增强区域，每个n掺杂的增强区域与p区域分离。
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