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    DEVICE STRUCTURES FOR A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR MANUFACTURED USING A HYBRID ORIENTATION TECHNOLOGY WAFER AND DESIGN STRUCTURES FOR A HIGH VOLTAGE INTEGRATED CIRCUIT
    3.
    发明申请
    DEVICE STRUCTURES FOR A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR MANUFACTURED USING A HYBRID ORIENTATION TECHNOLOGY WAFER AND DESIGN STRUCTURES FOR A HIGH VOLTAGE INTEGRATED CIRCUIT 失效
    使用混合方向技术制造的高电压场效应晶体管的器件结构和用于高压集成电路的设计结构

    公开(公告)号：US20090256174A1

    公开(公告)日：2009-10-15

    申请号：US12121286

    申请日：2008-05-15

    申请人： Renata Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Andreas D. Stricker

    发明人： Renata Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Andreas D. Stricker

    IPC分类号： H01L29/778

    CPC分类号： H01L29/808 ,  H01L29/0692

    摘要： Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer.

    摘要翻译： 高压结场效应晶体管的器件结构和高压集成电路的设计结构。 使用具有第一晶体取向的第一半导体层，具有第二晶体取向的第二半导体层和在第一和第二半导体层之间的绝缘层的混合定向技术晶片制造器件结构。 器件结构包括具有第二晶体取向的外延半导体区域和外延半导体区域中的第一和第二p-n结。 外延半导体区域从第二半导体层延伸穿过绝缘层和第一半导体层朝向第一半导体层的顶表面延伸。 第一和第二p-n结在第二半导体层和第一半导体层的顶表面之间的外延半导体区域内被深入布置。

    Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit
    4.
    发明授权
    Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit 失效
    使用混合取向技术晶圆制造的高压结场效应晶体管的器件结构和用于高压集成电路的设计结构

    公开(公告)号：US07791105B2

    公开(公告)日：2010-09-07

    申请号：US12121286

    申请日：2008-05-15

    申请人： Renata Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Andreas D. Stricker

    发明人： Renata Camillo-Castillo ,  Robert J. Gauthier, Jr. ,  Richard A. Phelps ,  Andreas D. Stricker

    IPC分类号： H01L29/778

    CPC分类号： H01L29/808 ,  H01L29/0692

    摘要： Device structures for a high voltage junction field effect transistor and design structures for a high voltage integrated circuit. The device structure is manufactured using a hybrid orientation technology wafer with a first semiconductor layer with a first crystalline orientation, a second semiconductor layer with a second crystalline orientation, and an insulating layer between the first and second semiconductor layers. The device structure includes an epitaxial semiconductor region having the second crystalline orientation and first and second p-n junctions in the epitaxial semiconductor region. The epitaxial semiconductor region extends from the second semiconductor layer through the insulating layer and the first semiconductor layer toward a top surface of the first semiconductor layer. The first and second p-n junctions are arranged in depth within the epitaxial semiconductor region between the second semiconductor layer and the top surface of the first semiconductor layer.

    摘要翻译： 高压结场效应晶体管的器件结构和高压集成电路的设计结构。 使用具有第一晶体取向的第一半导体层，具有第二晶体取向的第二半导体层和在第一和第二半导体层之间的绝缘层的混合定向技术晶片制造器件结构。 器件结构包括具有第二晶体取向的外延半导体区域和外延半导体区域中的第一和第二p-n结。 外延半导体区域从第二半导体层延伸穿过绝缘层和第一半导体层朝向第一半导体层的顶表面延伸。 第一和第二p-n结在第二半导体层和第一半导体层的顶表面之间的外延半导体区域内被深入布置。

    Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure
    7.
    发明授权
    Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure 有权
    具有侧壁限定的内在基极到外部基极连接区域的晶体管结构和形成该结构的方法

    公开(公告)号：US08405186B2

    公开(公告)日：2013-03-26

    申请号：US12817249

    申请日：2010-06-17

    申请人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

    发明人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

    IPC分类号： H01L21/70

    CPC分类号： H01L29/732 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7378

    摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.

    摘要翻译： 公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。 结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极 电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度 发射极层）进行选择性调整，以优化晶体管性能。

    TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE
    8.
    发明申请
    TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE 有权
    具有侧向定义的内部基极到极端基底连接区域的晶体管结构及形成结构的方法

    公开(公告)号：US20110309471A1

    公开(公告)日：2011-12-22

    申请号：US12817249

    申请日：2010-06-17

    申请人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

    发明人： Renata Camillo-Castillo ,  Mattias E. Dahlstrom ,  Peter B. Gray ,  David L. Harame ,  Russell T. Herrin ,  Alvin J. Joseph ,  Andreas D. Stricker

    IPC分类号： H01L29/73 ,  H01L21/331

    CPC分类号： H01L29/732 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7378

    摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.

    摘要翻译： 公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。 结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极 电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度 发射极层）进行选择性调整，以优化晶体管性能。

    Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time
    9.
    发明授权
    Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time 失效
    混合耐压静电放电保护可控硅整流器，增加开启时间

    公开(公告)号：US07005686B1

    公开(公告)日：2006-02-28

    申请号：US11161184

    申请日：2005-07-26

    申请人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad ,  Andreas D. Stricker ,  Min Woo

    发明人： Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad ,  Andreas D. Stricker ,  Min Woo

    IPC分类号： H01L29/66 ,  H01L21/33

    CPC分类号： H01L27/0262 ,  H01L29/87

    摘要： Disclosed is a method for increasing substrate resistance in a silicon controlled rectifier in order to decrease turn on time so that the silicon controlled rectifier may be used as an effective electrostatic discharge protection device to protect against HBM, MM and CDM discharge events. Additionally, disclosed is an improved SCR structure that is adapted for use as an electrostatic discharge device to protect against human body model events by delivering an electrostatic discharge current directly to a ground rail. The improved SCR structure incorporates various features for increasing substrate resistance and, thereby, for decreasing turn on time. These features include a second n-well that functions as an obstacle to current flow, a narrow current flow channel between co-planar buried n-bands connected to a lower portion of the second n-well, a zero threshold voltage area, and an external resistor electrically connected between the SCR and the ground rail.

    摘要翻译： 公开了一种用于增加可控硅整流器中的衬底电阻以减少导通时间的方法，使得可控硅整流器可以用作有效的静电放电保护装置，以防止HBM，MM和CDM放电事件。 此外，公开了一种改进的SCR结构，其适于用作静电放电装置，以通过将静电放电电流直接递送到接地轨来防止人体模型事件。 改进的SCR结构包含用于增加衬底电阻并因此减少导通时间的各种特征。 这些特征包括作为电流流动的障碍的第二n阱，连接到第二n阱的下部的共平面埋入n波段之间的窄电流流动通道，零阈值电压区域和 外部电阻电连接在SCR和接地导轨之间。