公开(公告)号：US08234594B2

公开(公告)日：2012-07-31

申请号：US11552225

申请日：2006-10-24

申请人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Jeanne P. Bickford ,  Markus Buehler ,  Jason D. Hibbeler ,  Juergen Koehl ,  Edward J. Nowak

IPC分类号： G06F17/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located at a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is approximately axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is approximately axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

摘要翻译： 一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和位于距离第二线的第一距离的第四线 在第二级线路上。 第一通孔在第二导线的第一位置连接第一和第二导线。 第二通孔在第一位置处连接第二和第三导线，第二通孔大致轴向对准第一通孔。 第三通过在第四线的第二位置连接第三和第四导线。 在第二位置连接第一和第四导线的第四通孔，第四通孔与第三通孔大致轴向对齐。 第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

公开(公告)号：US08232627B2

公开(公告)日：2012-07-31

申请号：US12563195

申请日：2009-09-21

申请人： Andres Bryant ,  Edward J. Nowak

发明人： Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L29/06

CPC分类号： H01L21/845 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211

摘要： Disclosed is an integrated circuit device having series-connected planar or non-planar field effect transistors (FETs) with integrated voltage equalization and a method of forming the device. The series-connected FETs comprise gates positioned along a semiconductor body to define the channel regions for the series-connected FETs. Source/drain regions are located within the semiconductor body on opposing sides of the channel regions such that each portion of the semiconductor body between adjacent gates comprises one source/drain region for one field effect transistor abutting another source/drain region for another field effect transistor. Integrated voltage equalization is achieved through a conformal conductive layer having a desired resistance and positioned over the series-connected FETs such that it is electrically isolated from the gates, but in contact with the source/drain regions within the semiconductor body.

摘要翻译： 公开了具有集成电压均衡的具有串联的平面或非平面场效应晶体管（FET）的集成电路器件和形成器件的方法。 串联连接的FET包括沿着半导体本体定位的门，以限定用于串联连接的FET的沟道区。 源极/漏极区域位于沟道区域的相对侧上的半导体本体内，使得相邻栅极之间的半导体本体的每个部分包括用于一个场效应晶体管的一个源极/漏极区域，用于与另一个场效应晶体管的另一个源极/漏极区域相邻接 。 集成电压均衡通过具有期望电阻的并行导电层实现，并且位于串联连接的FET上，使得其与栅极电隔离，但与半导体本体内的源极/漏极区域接触。

公开(公告)号：US20120181588A1

公开(公告)日：2012-07-19

申请号：US13005650

申请日：2011-01-13

申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, JR. ,  John J. Ellis-Monaghan ,  Edward J. Nowak

IPC分类号： H01L31/113 ,  G06F17/50 ,  H01L31/18

CPC分类号： H01L27/14614 ,  H01L27/14689

摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage.

摘要翻译： 像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。 像素传感器单元中的晶体管具有包括具有厚区域和薄区域的栅极电介质的栅极结构。 栅极结构的栅电极形成在栅极电介质的厚区域和栅极电介质的薄区域上。 栅极电介质的厚区域和栅极电介质的薄区为晶体管提供非对称阈值电压。

公开(公告)号：US20120168873A1

公开(公告)日：2012-07-05

申请号：US12984773

申请日：2011-01-05

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L21/70 ,  G06F17/50 ,  H01L21/8238

CPC分类号： H01L27/0922 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/66659

摘要： Transmission gates, methods of fabricating transmission gates, and design structures for a transmission gate. The transmission gate includes an n-channel field effect transistor characterized by terminals that are asymmetrically doped and a p-channel field effect transistor characterized by terminals that are asymmetrically doped.

摘要翻译： 传输门，制造传输门的方法和传输门的设计结构。 传输门包括n沟道场效应晶体管，其特征在于不对称掺杂的端子和由不对称掺杂的端子表征的p沟道场效应晶体管。

公开(公告)号：US20120156838A1

公开(公告)日：2012-06-21

申请号：US13406652

申请日：2012-02-28

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L21/8238

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： Disclosed are embodiments of a semiconductor structure that includes one or more multi-gate field effect transistors (MUGFETs), each MUGFET having one or more semiconductor fins. In the embodiments, dopant implant region is incorporated into the upper portion of the channel region of a semiconductor fin in order to selectively modify (i.e., decrease or increase) the threshold voltage within that upper portion relative to the threshold voltage in the lower portion and, thereby to selectively modify (i.e., decrease or increase) device drive current. In the case of a multiple semiconductor fins, the use of implant regions, the dopant conductivity type in the implant regions and/or the sizes of the implant regions can be varied from fin to fin within a multi-fin MUGFET or between different single and/or multi-fin MUGFETs so that individual device drive current can be optimized. Also disclosed herein are embodiments of a method of forming the semiconductor structure.

摘要翻译： 公开了包括一个或多个多栅极场效应晶体管（MUGFET）的半导体结构的实施例，每个MUGFET具有一个或多个半导体鳍片。 在实施例中，掺杂剂注入区域被并入到半导体鳍片的沟道区域的上部，以便相对于下部的阈值电压选择性地修改（即，降低或增加）该上部内的阈值电压） ，从而选择性地修改（即，减小或增加）器件驱动电流。 在多个半导体鳍片的情况下，注入区域，植入区域中的掺杂剂导电类型和/或植入区域的尺寸的使用可以在多翅片MUGFET内的翅片或鳍片之间或者在不同的单个和 /或多鳍MUGFET，使得可以优化单个设备驱动电流。 本文还公开了形成半导体结构的方法的实施例。

公开(公告)号：US20120098066A1

公开(公告)日：2012-04-26

申请号：US12909917

申请日：2010-10-22

申请人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/311

CPC分类号： H01L29/7855 ,  H01L21/3081 ,  H01L29/66795 ,  H01L29/785

摘要： A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure position on a substrate. The first rectangular fin structure has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The structure additionally includes a second rectangular fin structure position on the substrate. Similarly, the second rectangular fin structure also has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and is positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. Additionally, a gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The structure further includes a first cap on the top of the first rectangular fin structure. The first cap separates the gate conductor from the first rectangular fin structure.

摘要翻译： 一种方法和结构包括场效应晶体管结构，其包括在衬底上的第一矩形鳍结构位置。 第一矩形翅片结构具有接触基底的底部，与底部相对的顶部以及顶部和底部之间的边。 该结构还包括在基底上的第二矩形翅片结构位置。 类似地，第二矩形翅片结构还具有接触基底的底部，与底部相对的顶部以及顶部和底部之间的边。 第二矩形翅片结构的侧面平行于第一矩形翅片结构的侧面。 此外，沟槽绝缘体位于衬底上并且位于第一矩形翅片结构的侧面和第二矩形鳍结构的侧面之间。 此外，栅极导体位于沟槽绝缘体上，位于第一矩形翅片结构的侧面和顶部之上，并且位于第二矩形鳍结构的侧面和顶部之上。 栅极导体垂直于第一矩形翅片结构的侧面和第二矩形翅片结构的侧面延伸。 此外，栅极绝缘体位于栅极导体和第一矩形翅片结构之间以及栅极导体和第二矩形鳍结构之间。 该结构还包括在第一矩形翅片结构的顶部上的第一盖。 第一盖将栅极导体与第一矩形鳍结构分开。

公开(公告)号：US08158500B2

公开(公告)日：2012-04-17

申请号：US12694649

申请日：2010-01-27

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/94 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/785

摘要： An improved field effect transistors (FETs) and methods of manufacturing the field effect transistors (FETs) are provided. The method of manufacturing a zero capacitance random access memory cell (ZRAM) includes comprises forming a finFET on a substrate and enhancing a storage capacitance of the finFET. The enhancement can be by either adding a storage capacity to the finFET or altering a portion of the finFET after formation of a fin body of the finFET.

摘要翻译： 提供改进的场效应晶体管（FET）和制造场效应晶体管（FET）的方法。 制造零电容随机存取存储单元（ZRAM）的方法包括在衬底上形成finFET并增强finFET的存储电容。 增强可以通过在finFET的翅片体形成之后向finFET添加存储容量或者改变finFET的一部分。

公开(公告)号：US20120068233A1

公开(公告)日：2012-03-22

申请号：US12886639

申请日：2010-09-21

申请人： Brent A. Anderson ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of forming a field effect transistor and a field effect transistor. The method includes (a) forming gate stack on a silicon layer of a substrate; (b) forming two or more SiGe filled trenches in the silicon layer on at least one side of the gate stack, adjacent pairs of the two or more SiGe filled trenches separated by respective silicon regions of the silicon layer; and (c) forming source/drains in the silicon layer on opposite sides of the gate stack, the source/drains abutting a channel region of the silicon layer under the gate stack.

摘要翻译： 一种形成场效应晶体管和场效应晶体管的方法。 该方法包括（a）在衬底的硅层上形成栅叠层; （b）在所述栅极堆叠的至少一侧的所述硅层中形成两个或更多个SiGe填充的沟槽，所述相邻的两个或更多个SiGe填充的沟槽对由所述硅层的相应硅区分隔; 和（c）在栅极堆叠的相对侧的硅层中形成源极/漏极，源极/漏极邻接栅极叠层下方的硅层的沟道区域。

公开(公告)号：US08106455B2

公开(公告)日：2012-01-31

申请号：US12432927

申请日：2009-04-30

申请人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

发明人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

摘要翻译： 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

公开(公告)号：US20110312143A1

公开(公告)日：2011-12-22

申请号：US13220753

申请日：2011-08-30

申请人： Alberto Escobar ,  Brian J. Greene ,  Edward J. Nowak

发明人： Alberto Escobar ,  Brian J. Greene ,  Edward J. Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L29/66575 ,  H01L29/7849

摘要： Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor.

摘要翻译： 公开了具有降低的驱动电流温度灵敏度的场效应晶体管（FET）的实施例。 具体地说，通过与应变相关的载流子迁移率变化相反的FET通道区域中任何温度依赖的载流子迁移率变化被同时抵消，以确保驱动电流响应于温度变化保持近似恒定或至少在预定范围内。 这种相反的应变依赖性载流子迁移率变化由应变结构提供，该应变结构被配置为在通道区域上赋予预选的应变类型的温度相关量。 还公开了形成场效应晶体管的相关方法的实施例。