公开(公告)号：US10289178B1

公开(公告)日：2019-05-14

申请号：US15479176

申请日：2017-04-04

Applicant: Xilinx, Inc.

Inventor： Adrian Lynam ,  John K. Jennings ,  Umanath R. Kamath ,  Michael J. Hart ,  James Karp

IPC: G01R19/00 ,  G06F1/20 ,  G05F1/46 ,  H03K17/22 ,  H03K19/003 ,  G01R19/165 ,  G01K13/00

Abstract: Methods and apparatus are described for detecting both single event latch-up (SEL) and electrical overvoltage stress (EOS) using a single, reconfigurable detection circuit. One example circuit capable of detecting a latch-up state and an overvoltage condition generally includes an impedance element coupled to a power supply node; a voltage divider coupled to the power supply node; a multiplexer having a first input coupled to a tap of the voltage divider, a second input coupled to a first portion of the impedance element, and a third input coupled to a second portion of the impedance element; a reference generator; and an analog-to-digital converter (ADC) having a first input coupled to an output of the multiplexer and a second input coupled to an output of the reference generator.

公开(公告)号：US20180356294A1

公开(公告)日：2018-12-13

申请号：US15616765

申请日：2017-06-07

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  Padraig Kelly ,  John K. Jennings

IPC: G01K7/01 ,  H03K19/003 ,  H03K19/0175

CPC classification number: G01K7/01 ,  G01K1/026 ,  G01K7/015 ,  H03K19/00307 ,  H03K19/017581

Abstract: An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.

公开(公告)号：US20180074533A1

公开(公告)日：2018-03-15

申请号：US15266947

申请日：2016-09-15

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  John K. Jennings

IPC: G05F1/46

CPC classification number: G05F1/468

Abstract: An integrated circuit includes a reference voltage circuit. The reference voltage circuit includes a bipolar junction transistor (BJT) configured to receive a first current during a first phase of a clock cycle to generate a first base-emitter junction voltage, and receive a second current during a second phase of the clock cycle to generate a second base-emitter junction voltage. The reference voltage circuit includes a switched capacitor circuit configured to provide a reference voltage associated with the first base-emitter junction voltage and the second base-emitter junction voltage.

公开(公告)号：US09793899B1

公开(公告)日：2017-10-17

申请号：US15382385

申请日：2016-12-16

Applicant: Xilinx, Inc.

Inventor： Pierre Maillard ,  Jue Arver ,  Michael J. Hart ,  John K. Jennings

IPC: H03K19/003 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/0033

Abstract: The disclosed IC includes a load circuit and a temperature sensor circuit. The temperature sensor circuit measures temperature of the IC and stores temperature data in a register. An SEL mitigation circuit monitors the IC for a temperature change indicative of an SEL. A temperature change greater than a threshold over a time interval is indicative of an SEL. The SEL mitigation circuit is configured to reduce voltage applied to the IC to a voltage level that clears an SEL in the IC in response to a temperature change exceeding the threshold and to increase voltage applied to the load circuit after the reduction in voltage.

公开(公告)号：US09503058B1

公开(公告)日：2016-11-22

申请号：US14629816

申请日：2015-02-24

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  John K. Jennings ,  Edward Cullen

IPC: H03K3/011 ,  H03L7/00 ,  H03K3/0231 ,  G06F1/08

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  H03K3/0231 ,  H03L1/00 ,  H03L1/022 ,  H03L7/00 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: Various example implementations are directed to circuits and methods for generating a clock signal. According to an example embodiment, a circuit arrangement includes a relaxation oscillator configured to output a clock signal. The clock signal has an oscillation frequency dependent on a reference current provided to the relaxation oscillator, an operating temperature of the relaxation oscillator, and a supply voltage used to power the relaxation oscillator. The circuit arrangement also includes a current source coupled to the relaxation oscillator and configured to generate the reference current. The current source is configured to adjust the reference current, in response to a change in one or more of the temperature of the relaxation oscillator and the supply voltage, to inhibit change in the oscillation frequency of the clock signal.

Abstract translation: 各种示例实现涉及用于产生时钟信号的电路和方法。 根据示例性实施例，电路装置包括配置成输出时钟信号的张弛振荡器。 时钟信号具有取决于提供给张弛振荡器的参考电流，张弛振荡器的操作温度和用于为张弛振荡器供电的电源电压的振荡频率。 电路装置还包括耦合到张弛振荡器并被配置为产生参考电流的电流源。 电流源被配置为响应于张弛振荡器的温度和电源电压中的一个或多个的变化来调整参考电流，以抑制时钟信号的振荡频率的变化。

公开(公告)号：US20160097805A1

公开(公告)日：2016-04-07

申请号：US14505240

申请日：2014-10-02

Applicant: Xilinx, Inc

Inventor： Ping-Chin Yeh ,  John K. Jennings ,  Rhesa Nathanael ,  Nui Chong ,  Cheang-Whang Chang ,  Daniel Y. Chung

IPC: G01R31/28

CPC classification number: G01R31/2851 ,  G01R31/2837 ,  G01R31/2843 ,  G01R31/3167

Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

Abstract translation: 在示例实现中，集成电路（IC）包括：设置在IC的管芯上的多个位置中的多个晶体管; 耦合到所述多个晶体管中的每一个的端子的导体; 耦合到所述导体的数模转换器（DAC），以响应于数字输入将电压信号驱动到所述多个晶体管; 以及耦合到所述导体的至少一部分的模数转换器（ADC），以响应于所述电压信号而响应于在所述多个晶体管中感应的电流信号而生成样本，所述样本至少指示 一个静电特性用于多个晶体管。

公开(公告)号：US10756748B1

公开(公告)日：2020-08-25

申请号：US16396257

申请日：2019-04-26

Applicant: Xilinx, Inc.

Inventor： Prathamesh M. Khatavkar ,  John K. Jennings ,  Alonso Morgado

IPC: H03M1/12 ,  H03M1/46 ,  H03K5/24 ,  H01L29/94 ,  H03H19/00 ,  H01L49/02

Abstract: Apparatus and associated methods relate to a circuit that is configured to keep a comparator input voltage stable. In an illustrative example, the circuit may include a first differential path coupled to a first switched-capacitor network's output, a second differential path coupled to a second switched-capacitor network's output. A comparator may have a first input coupled to the first differential path and a second input coupled to the second differential path. The comparator may be controlled by a clock signal to perform comparison. A first capacitor may be coupled from the clock signal to the first differential signal path and a second capacitor may be coupled from the clock signal to the second differential signal path. By introducing the first capacitor and the second capacitor, the comparator input common-mode may keep stable, and the comparator may be less sensitive to kickback effects.

公开(公告)号：US10608630B1

公开(公告)日：2020-03-31

申请号：US16019150

申请日：2018-06-26

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  Diarmuid Collins ,  John K. Jennings

IPC: H03K17/687 ,  H03K17/16 ,  G05F1/44 ,  H03M1/34

Abstract: A complementary metal-oxide-semiconductor (CMOS) switching system with increased supply rejection is disclosed. The system comprises a voltage regulator and a CMOS circuit. The voltage regulator receives a supply voltage and generates a regulated voltage by regulating an amplitude of the received supply voltage. The CMOS circuit includes an input terminal to receive a first voltage, switching circuitry to selectively couple the CMOS circuit to the voltage regulator in one of a plurality of configurations, and an output terminal to output a second voltage based at least in part on the first voltage and the regulated voltage when the CMOS circuit is coupled to the voltage regulator in a first configuration of the plurality of configurations.

公开(公告)号：US10379155B2

公开(公告)日：2019-08-13

申请号：US14505240

申请日：2014-10-02

Applicant: Xilinx, Inc

Inventor： Ping-Chin Yeh ,  John K. Jennings ,  Rhesa Nathanael ,  Nui Chong ,  Cheang-Whang Chang ,  Daniel Y Chung

IPC: G01R31/28 ,  G01R31/3167

Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.

公开(公告)号：US10236873B2

公开(公告)日：2019-03-19

申请号：US14659747

申请日：2015-03-17

Applicant: Xilinx, Inc.

Inventor： Ionut C. Cical ,  John K. Jennings ,  Chandrika Durbha

IPC: H03K17/16 ,  H03K17/06 ,  H03K3/012

Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage. A control circuit is coupled to the analog switch to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.